URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [tags/] [Release_1.1/] [sim/] [src/] - Rev 80

Rev	Log message	Author	Age	Path
80	renamed to version 1.1 to follow the versioning system	JonasDC	4066d 08h	/mod_sim_exp/tags/Release_1.1/sim/src/
49	First full stable version with documentation. Includes flexible pipeline design, PLB interface and the RAM and FIFO is still using xilinx primitives.	JonasDC	4106d 09h	/mod_sim_exp/tags/Release_1.1/sim/src/
35	new test values, 1st exponentiation gives error on result with new pipeline commit for test purposes	JonasDC	4198d 07h	/mod_sim_exp/tags/Release_1.1/sim/src/
27	test input values for multiplier_tb	JonasDC	4199d 08h	/mod_sim_exp/tags/Release_1.1/sim/src/
3	updated vhdl sources with new header according to OC design rules and formated code added makefile and simulation input file for testbench simulation	JonasDC	4214d 08h	/mod_sim_exp/tags/Release_1.1/sim/src/