URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [tags/] [Release_1.3/] - Rev 87

Rev	Log message	Author	Age	Path
55	updated resource usage in comments	JonasDC	4083d 08h	/mod_sim_exp/tags/Release_1.3/
54	generic fifo design: correctrly inferred by xilinx and altera	JonasDC	4083d 08h	/mod_sim_exp/tags/Release_1.3/
53	correctly inferred ram for altera dual port ram	JonasDC	4083d 14h	/mod_sim_exp/tags/Release_1.3/
52	correct inferring of blockram, no additional resources.	JonasDC	4083d 15h	/mod_sim_exp/tags/Release_1.3/
51	true dual port ram for xilinx	JonasDC	4083d 16h	/mod_sim_exp/tags/Release_1.3/
50	added folder for ram descriptions added experimental simple dual port ram implementation for xilinx	JonasDC	4083d 16h	/mod_sim_exp/tags/Release_1.3/
47	added documentation for the IP core.	JonasDC	4163d 15h	/mod_sim_exp/tags/Release_1.3/
46	chance run_auto port or mod_sim_exp_core to exp_m	JonasDC	4163d 16h	/mod_sim_exp/tags/Release_1.3/
45	chance run_auto port or mod_sim_exp_core to exp_m	JonasDC	4163d 16h	/mod_sim_exp/tags/Release_1.3/
44	toplevel of the Modular Simultaneous Exponentiation IP core for the PLB interface	JonasDC	4167d 09h	/mod_sim_exp/tags/Release_1.3/