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[/] [mod_sim_exp/] [tags/] [Release_1.4/] - Rev 98

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93 Tag for Version 1.4 of The Modular Simulataneous Exponentiation Core. This version adds support for the AXI4-Lite bus interface. JonasDC 3959d 16h /mod_sim_exp/tags/Release_1.4/
92 updated documentation with minor interrupt changes of AXI interface JonasDC 3959d 16h /mod_sim_exp/trunk/
91 changed interrupt structure of AXI4-Lite interface. Now the interrupt has to be acknowledged by clearing the appropriate interrupt source flag in the control register. JonasDC 3961d 19h /mod_sim_exp/trunk/
90 reverted changes from previous revision, updated AXI version with testbench JonasDC 3963d 10h /mod_sim_exp/trunk/
89 updated vhdl files so now different clock frequencies are posible for the core and bus interface. JonasDC 4027d 08h /mod_sim_exp/trunk/
88 small update on documentation, changed fault in axi control_reg JonasDC 4033d 09h /mod_sim_exp/trunk/
87 updated documentation to version 1.4
core now supports the AXI4-Lite bus
JonasDC 4033d 10h /mod_sim_exp/trunk/
86 update on previous JonasDC 4033d 10h /mod_sim_exp/trunk/
85 changed so that reset now also affects slave register JonasDC 4033d 10h /mod_sim_exp/trunk/
84 AXI-Lite interface updated, now tested and verified on Xilinx FPGA
renamed C_DEVICE parameter, because of conflicts with restricted parameter in xilinx XPS
JonasDC 4034d 18h /mod_sim_exp/trunk/
83 now using values from mod_sim_exp_pkg instead of direct entity JonasDC 4036d 19h /mod_sim_exp/trunk/
82 added first version of axi-lite interface and testbench for basic axi-lite operations, now under test JonasDC 4053d 15h /mod_sim_exp/trunk/
81 updated files, now using the components of the mod_sim_exp_pkg instead of direct entity declaration JonasDC 4053d 15h /mod_sim_exp/trunk/
78 updated documentation with new RAM style information JonasDC 4063d 09h /mod_sim_exp/trunk/
77 found fault in code, now synthesizes normally JonasDC 4069d 07h /mod_sim_exp/trunk/
76 testbench update JonasDC 4071d 18h /mod_sim_exp/trunk/
75 made rw_address a vector of a fixed width JonasDC 4071d 18h /mod_sim_exp/trunk/
74 removed C_NR_OP and C_NR_M from the generic of mod_sim_exp_core and made them contstants, because currently no other values than 4 an 2 resp. are supported/can be implemented. JonasDC 4074d 14h /mod_sim_exp/trunk/
73 updated plb interface, mem_style and device generics added JonasDC 4075d 13h /mod_sim_exp/trunk/
72 deleted old resources JonasDC 4076d 13h /mod_sim_exp/trunk/
71 added synthesis report for altera and xilinx for the new ram.
added coregen sources for xilinx for primitive RAM
JonasDC 4076d 13h /mod_sim_exp/trunk/
70 updated testbench for use with new core parameters
updated makefile, added new sources
JonasDC 4076d 13h /mod_sim_exp/trunk/
69 big update, the mod_sim_exp core now has a selectable ram structure. a generic ram that should be usable in any fpga, a asymmetric ram that is usable for some devices of altera or xilinx and uses less resources. JonasDC 4076d 13h /mod_sim_exp/trunk/
67 added memory modules for modulus and operands for FPGA's that support asymmetric memory inferring. JonasDC 4076d 16h /mod_sim_exp/trunk/
66 added asymmetric ram structures to support a more performant ramstyle.
defined for xilinx and altera, not tested with other tools.
JonasDC 4076d 17h /mod_sim_exp/trunk/
65 updated plb interface, now modulus is selectable and, fifo depth is adjustable.
updated makefile with new sources and update component in package
JonasDC 4084d 08h /mod_sim_exp/trunk/
64 added synthesis reports of xilinx and altera JonasDC 4084d 14h /mod_sim_exp/trunk/
63 now using a generic description of the ram for the memory. the core now should synthesize for al fpga's, no device specific code anymore. tested and synthesizes for altera and xilinx JonasDC 4084d 14h /mod_sim_exp/trunk/
62 not used anymore JonasDC 4084d 17h /mod_sim_exp/trunk/
61 updated comments, added optional altera constraint JonasDC 4084d 17h /mod_sim_exp/trunk/

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