OpenCores
URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [tags/] [Release_1.4/] [sim/] - Rev 93

Rev

Filtering Options

Clear current filter

Rev Log message Author Age Path
93 Tag for Version 1.4 of The Modular Simulataneous Exponentiation Core. This version adds support for the AXI4-Lite bus interface. JonasDC 3959d 20h /mod_sim_exp/tags/Release_1.4/sim/
90 reverted changes from previous revision, updated AXI version with testbench JonasDC 3963d 14h /mod_sim_exp/trunk/sim/
84 AXI-Lite interface updated, now tested and verified on Xilinx FPGA
renamed C_DEVICE parameter, because of conflicts with restricted parameter in xilinx XPS
JonasDC 4034d 22h /mod_sim_exp/trunk/sim/
70 updated testbench for use with new core parameters
updated makefile, added new sources
JonasDC 4076d 17h /mod_sim_exp/trunk/sim/
65 updated plb interface, now modulus is selectable and, fifo depth is adjustable.
updated makefile with new sources and update component in package
JonasDC 4084d 12h /mod_sim_exp/trunk/sim/
41 removed deprecated files from version control JonasDC 4181d 20h /mod_sim_exp/trunk/sim/
35 new test values, 1st exponentiation gives error on result with new pipeline
commit for test purposes
JonasDC 4195d 12h /mod_sim_exp/trunk/sim/
31 put first cell logic of the pipeline in a separate design unit, tested and working JonasDC 4195d 23h /mod_sim_exp/trunk/sim/
30 put last cell logic of the pipeline in a separate design unit, tested and working JonasDC 4195d 23h /mod_sim_exp/trunk/sim/
28 updated makefile for new pipeline sources JonasDC 4196d 13h /mod_sim_exp/trunk/sim/
27 test input values for multiplier_tb JonasDC 4196d 13h /mod_sim_exp/trunk/sim/
24 changed names of top-level module to mod_sim_exp_core JonasDC 4199d 22h /mod_sim_exp/trunk/sim/
11 simulation output folder JonasDC 4210d 16h /mod_sim_exp/trunk/sim/
5 not needed on svn, is generated by testbench JonasDC 4210d 22h /mod_sim_exp/trunk/sim/
3 updated vhdl sources with new header according to OC design rules and formated code
added makefile and simulation input file for testbench simulation
JonasDC 4211d 13h /mod_sim_exp/trunk/sim/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.