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[/] [mod_sim_exp/] [tags/] [Release_1.4] - Rev 93

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Rev	Log message	Author	Age	Path
71	added synthesis report for altera and xilinx for the new ram. added coregen sources for xilinx for primitive RAM	JonasDC	4074d 05h	/mod_sim_exp/tags/Release_1.4
70	updated testbench for use with new core parameters updated makefile, added new sources	JonasDC	4074d 05h	/mod_sim_exp/tags/Release_1.4
69	big update, the mod_sim_exp core now has a selectable ram structure. a generic ram that should be usable in any fpga, a asymmetric ram that is usable for some devices of altera or xilinx and uses less resources.	JonasDC	4074d 05h	/mod_sim_exp/tags/Release_1.4
67	added memory modules for modulus and operands for FPGA's that support asymmetric memory inferring.	JonasDC	4074d 08h	/mod_sim_exp/tags/Release_1.4
66	added asymmetric ram structures to support a more performant ramstyle. defined for xilinx and altera, not tested with other tools.	JonasDC	4074d 09h	/mod_sim_exp/tags/Release_1.4
65	updated plb interface, now modulus is selectable and, fifo depth is adjustable. updated makefile with new sources and update component in package	JonasDC	4082d 00h	/mod_sim_exp/tags/Release_1.4
64	added synthesis reports of xilinx and altera	JonasDC	4082d 06h	/mod_sim_exp/tags/Release_1.4
63	now using a generic description of the ram for the memory. the core now should synthesize for al fpga's, no device specific code anymore. tested and synthesizes for altera and xilinx	JonasDC	4082d 06h	/mod_sim_exp/tags/Release_1.4
62	not used anymore	JonasDC	4082d 09h	/mod_sim_exp/tags/Release_1.4
61	updated comments, added optional altera constraint	JonasDC	4082d 09h	/mod_sim_exp/tags/Release_1.4

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