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Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [tags/] [Release_1.5/] [bench/] [vhdl/] - Rev 104

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Rev	Log message	Author	Age	Path
104	Release of version 1.5, this version supports an independent clock for the multiplier	JonasDC	3907d 17h	/mod_sim_exp/tags/Release_1.5/bench/vhdl/
94	BIG update: core now supports different clock speed for the multiplier core, so more performance is posible. currently this version is working in simulation and is being tested on hardware. Changes in this update include: - changed RAM and memory to support different clocks - new FIFO that supports dual clock (slightly modified version of generic_fifo's on OpenCores.org) - parameter C_FIFO_DEPTH is now replace by C_FIFO_AW (address width of the fifo pointers) - added logic for control signals to cross from one clock domain to another - updated testbenches and interfaces accordingly - added log of synthesis of the 2 new fifo's for Xilinx	JonasDC	3956d 18h	/mod_sim_exp/tags/Release_1.5/bench/vhdl/
90	reverted changes from previous revision, updated AXI version with testbench	JonasDC	3962d 17h	/mod_sim_exp/tags/Release_1.5/bench/vhdl/
84	AXI-Lite interface updated, now tested and verified on Xilinx FPGA renamed C_DEVICE parameter, because of conflicts with restricted parameter in xilinx XPS	JonasDC	4034d 01h	/mod_sim_exp/tags/Release_1.5/bench/vhdl/
82	added first version of axi-lite interface and testbench for basic axi-lite operations, now under test	JonasDC	4052d 22h	/mod_sim_exp/tags/Release_1.5/bench/vhdl/
76	testbench update	JonasDC	4071d 01h	/mod_sim_exp/tags/Release_1.5/bench/vhdl/
70	updated testbench for use with new core parameters updated makefile, added new sources	JonasDC	4075d 20h	/mod_sim_exp/tags/Release_1.5/bench/vhdl/
46	chance run_auto port or mod_sim_exp_core to exp_m	JonasDC	4170d 22h	/mod_sim_exp/tags/Release_1.5/bench/vhdl/
43	made the core parameters generics	JonasDC	4174d 15h	/mod_sim_exp/tags/Release_1.5/bench/vhdl/
37	changed names of some generics of the multiplier. moved the parameters for the core to the package of the core testbench now uses this parameters to adapt to different bit widths and new systolic pipeline now supports split or single pipeline	JonasDC	4193d 17h	/mod_sim_exp/tags/Release_1.5/bench/vhdl/
26	testbench for only the montgommery multiplier	JonasDC	4195d 16h	/mod_sim_exp/tags/Release_1.5/bench/vhdl/
24	changed names of top-level module to mod_sim_exp_core	JonasDC	4199d 01h	/mod_sim_exp/tags/Release_1.5/bench/vhdl/
3	updated vhdl sources with new header according to OC design rules and formated code added makefile and simulation input file for testbench simulation	JonasDC	4210d 16h	/mod_sim_exp/tags/Release_1.5/bench/vhdl/
2	First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules..	JonasDC	4214d 22h	/mod_sim_exp/tags/Release_1.5/bench/vhdl/

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