URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [tags/] [Release_1.5/] [rtl/] - Rev 104

Rev	Log message	Author	Age	Path
65	updated plb interface, now modulus is selectable and, fifo depth is adjustable. updated makefile with new sources and update component in package	JonasDC	4084d 21h	/mod_sim_exp/tags/Release_1.5/rtl/
63	now using a generic description of the ram for the memory. the core now should synthesize for al fpga's, no device specific code anymore. tested and synthesizes for altera and xilinx	JonasDC	4085d 03h	/mod_sim_exp/tags/Release_1.5/rtl/
62	not used anymore	JonasDC	4085d 06h	/mod_sim_exp/tags/Release_1.5/rtl/
61	updated comments, added optional altera constraint	JonasDC	4085d 06h	/mod_sim_exp/tags/Release_1.5/rtl/
60	generic version of the fifo, not device specific anymore, uses dpram_generic updated comments of RAM templates.	JonasDC	4087d 20h	/mod_sim_exp/tags/Release_1.5/rtl/
59	added templates that correctly infer RAM, for dual port en true dual port RAM added general functions file, (used in the two RAM templates)	JonasDC	4087d 20h	/mod_sim_exp/tags/Release_1.5/rtl/
55	updated resource usage in comments	JonasDC	4091d 20h	/mod_sim_exp/tags/Release_1.5/rtl/
54	generic fifo design: correctrly inferred by xilinx and altera	JonasDC	4091d 20h	/mod_sim_exp/tags/Release_1.5/rtl/
53	correctly inferred ram for altera dual port ram	JonasDC	4092d 03h	/mod_sim_exp/tags/Release_1.5/rtl/
52	correct inferring of blockram, no additional resources.	JonasDC	4092d 03h	/mod_sim_exp/tags/Release_1.5/rtl/