| Rev |
Log message |
Author |
Age |
Path |
| 104 |
Release of version 1.5, this version supports an independent clock for the multiplier |
JonasDC |
3923d 20h |
/mod_sim_exp/tags/Release_1.5/rtl/vhdl/core/ |
| 97 |
changes in makefile, and fifo's are now also in mod_sim_exp library |
JonasDC |
3959d 01h |
/mod_sim_exp/tags/Release_1.5/rtl/vhdl/core/ |
| 95 |
new control logic for the core, allow for greater frequencies for the multiplier.
changes:
- autorun_cntrl: the bit selection for the exponents is now implemented with a shift register in stead of a mux. credits to Geoffrey Ottoy for new design structure.
- mont_cntrl: gave the databus from and to the RAM more time to settle. data now has 3 clocks to get to its destination. |
JonasDC |
3960d 01h |
/mod_sim_exp/tags/Release_1.5/rtl/vhdl/core/ |
| 94 |
BIG update: core now supports different clock speed for the multiplier core, so more performance is posible. currently this version is working in simulation and is being tested on hardware. Changes in this update include:
- changed RAM and memory to support different clocks
- new FIFO that supports dual clock (slightly modified version of generic_fifo's on OpenCores.org)
- parameter C_FIFO_DEPTH is now replace by C_FIFO_AW (address width of the fifo pointers)
- added logic for control signals to cross from one clock domain to another
- updated testbenches and interfaces accordingly
- added log of synthesis of the 2 new fifo's for Xilinx |
JonasDC |
3972d 21h |
/mod_sim_exp/tags/Release_1.5/rtl/vhdl/core/ |
| 90 |
reverted changes from previous revision, updated AXI version with testbench |
JonasDC |
3978d 20h |
/mod_sim_exp/tags/Release_1.5/rtl/vhdl/core/ |
| 89 |
updated vhdl files so now different clock frequencies are posible for the core and bus interface. |
JonasDC |
4042d 18h |
/mod_sim_exp/tags/Release_1.5/rtl/vhdl/core/ |
| 84 |
AXI-Lite interface updated, now tested and verified on Xilinx FPGA
renamed C_DEVICE parameter, because of conflicts with restricted parameter in xilinx XPS |
JonasDC |
4050d 04h |
/mod_sim_exp/tags/Release_1.5/rtl/vhdl/core/ |
| 83 |
now using values from mod_sim_exp_pkg instead of direct entity |
JonasDC |
4052d 05h |
/mod_sim_exp/tags/Release_1.5/rtl/vhdl/core/ |
| 81 |
updated files, now using the components of the mod_sim_exp_pkg instead of direct entity declaration |
JonasDC |
4069d 01h |
/mod_sim_exp/tags/Release_1.5/rtl/vhdl/core/ |
| 75 |
made rw_address a vector of a fixed width |
JonasDC |
4087d 04h |
/mod_sim_exp/tags/Release_1.5/rtl/vhdl/core/ |
| 74 |
removed C_NR_OP and C_NR_M from the generic of mod_sim_exp_core and made them contstants, because currently no other values than 4 an 2 resp. are supported/can be implemented. |
JonasDC |
4090d 00h |
/mod_sim_exp/tags/Release_1.5/rtl/vhdl/core/ |
| 69 |
big update, the mod_sim_exp core now has a selectable ram structure. a generic ram that should be usable in any fpga, a asymmetric ram that is usable for some devices of altera or xilinx and uses less resources. |
JonasDC |
4091d 23h |
/mod_sim_exp/tags/Release_1.5/rtl/vhdl/core/ |
| 67 |
added memory modules for modulus and operands for FPGA's that support asymmetric memory inferring. |
JonasDC |
4092d 02h |
/mod_sim_exp/tags/Release_1.5/rtl/vhdl/core/ |
| 65 |
updated plb interface, now modulus is selectable and, fifo depth is adjustable.
updated makefile with new sources and update component in package |
JonasDC |
4099d 18h |
/mod_sim_exp/tags/Release_1.5/rtl/vhdl/core/ |
| 63 |
now using a generic description of the ram for the memory. the core now should synthesize for al fpga's, no device specific code anymore. tested and synthesizes for altera and xilinx |
JonasDC |
4100d 00h |
/mod_sim_exp/tags/Release_1.5/rtl/vhdl/core/ |
| 60 |
generic version of the fifo, not device specific anymore, uses dpram_generic
updated comments of RAM templates. |
JonasDC |
4102d 17h |
/mod_sim_exp/tags/Release_1.5/rtl/vhdl/core/ |
| 59 |
added templates that correctly infer RAM, for dual port en true dual port RAM
added general functions file, (used in the two RAM templates) |
JonasDC |
4102d 17h |
/mod_sim_exp/tags/Release_1.5/rtl/vhdl/core/ |
| 55 |
updated resource usage in comments |
JonasDC |
4106d 17h |
/mod_sim_exp/tags/Release_1.5/rtl/vhdl/core/ |
| 54 |
generic fifo design: correctrly inferred by xilinx and altera |
JonasDC |
4106d 17h |
/mod_sim_exp/tags/Release_1.5/rtl/vhdl/core/ |
| 45 |
chance run_auto port or mod_sim_exp_core to exp_m |
JonasDC |
4187d 01h |
/mod_sim_exp/tags/Release_1.5/rtl/vhdl/core/ |
