Rev |
Log message |
Author |
Age |
Path |
77 |
found fault in code, now synthesizes normally |
JonasDC |
4082d 23h |
/mod_sim_exp/tags/Release_1.5 |
76 |
testbench update |
JonasDC |
4085d 10h |
/mod_sim_exp/tags/Release_1.5 |
75 |
made rw_address a vector of a fixed width |
JonasDC |
4085d 10h |
/mod_sim_exp/tags/Release_1.5 |
74 |
removed C_NR_OP and C_NR_M from the generic of mod_sim_exp_core and made them contstants, because currently no other values than 4 an 2 resp. are supported/can be implemented. |
JonasDC |
4088d 06h |
/mod_sim_exp/tags/Release_1.5 |
73 |
updated plb interface, mem_style and device generics added |
JonasDC |
4089d 05h |
/mod_sim_exp/tags/Release_1.5 |
72 |
deleted old resources |
JonasDC |
4090d 05h |
/mod_sim_exp/tags/Release_1.5 |
71 |
added synthesis report for altera and xilinx for the new ram.
added coregen sources for xilinx for primitive RAM |
JonasDC |
4090d 05h |
/mod_sim_exp/tags/Release_1.5 |
70 |
updated testbench for use with new core parameters
updated makefile, added new sources |
JonasDC |
4090d 05h |
/mod_sim_exp/tags/Release_1.5 |
69 |
big update, the mod_sim_exp core now has a selectable ram structure. a generic ram that should be usable in any fpga, a asymmetric ram that is usable for some devices of altera or xilinx and uses less resources. |
JonasDC |
4090d 05h |
/mod_sim_exp/tags/Release_1.5 |
67 |
added memory modules for modulus and operands for FPGA's that support asymmetric memory inferring. |
JonasDC |
4090d 08h |
/mod_sim_exp/tags/Release_1.5 |
66 |
added asymmetric ram structures to support a more performant ramstyle.
defined for xilinx and altera, not tested with other tools. |
JonasDC |
4090d 09h |
/mod_sim_exp/tags/Release_1.5 |
65 |
updated plb interface, now modulus is selectable and, fifo depth is adjustable.
updated makefile with new sources and update component in package |
JonasDC |
4098d 00h |
/mod_sim_exp/tags/Release_1.5 |
64 |
added synthesis reports of xilinx and altera |
JonasDC |
4098d 06h |
/mod_sim_exp/tags/Release_1.5 |
63 |
now using a generic description of the ram for the memory. the core now should synthesize for al fpga's, no device specific code anymore. tested and synthesizes for altera and xilinx |
JonasDC |
4098d 06h |
/mod_sim_exp/tags/Release_1.5 |
62 |
not used anymore |
JonasDC |
4098d 09h |
/mod_sim_exp/tags/Release_1.5 |
61 |
updated comments, added optional altera constraint |
JonasDC |
4098d 09h |
/mod_sim_exp/tags/Release_1.5 |
60 |
generic version of the fifo, not device specific anymore, uses dpram_generic
updated comments of RAM templates. |
JonasDC |
4100d 23h |
/mod_sim_exp/tags/Release_1.5 |
59 |
added templates that correctly infer RAM, for dual port en true dual port RAM
added general functions file, (used in the two RAM templates) |
JonasDC |
4100d 23h |
/mod_sim_exp/tags/Release_1.5 |
55 |
updated resource usage in comments |
JonasDC |
4104d 23h |
/mod_sim_exp/tags/Release_1.5 |
54 |
generic fifo design: correctrly inferred by xilinx and altera |
JonasDC |
4104d 23h |
/mod_sim_exp/tags/Release_1.5 |