URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] - Rev 28

Rev	Log message	Author	Age	Path
8	added descriptive comments	JonasDC	4210d 19h	/mod_sim_exp/trunk/
7	Modified the architecture, no longer uses Xilinx primitive, instead generic instantiation added descriptive comments	JonasDC	4210d 19h	/mod_sim_exp/trunk/
6	Modified the architecture, no longer uses Xilinx primitive, instead generic instantiation added descriptive comments	JonasDC	4210d 19h	/mod_sim_exp/trunk/
5	not needed on svn, is generated by testbench	JonasDC	4210d 20h	/mod_sim_exp/trunk/
4	Modified the architecture, no longer uses Xilinx primitive, instead generic instantiation added descriptive comments	JonasDC	4210d 21h	/mod_sim_exp/trunk/
3	updated vhdl sources with new header according to OC design rules and formated code added makefile and simulation input file for testbench simulation	JonasDC	4211d 11h	/mod_sim_exp/trunk/
2	First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules..	JonasDC	4215d 17h	/mod_sim_exp/trunk/
1	The project and the structure was created	root	4217d 17h	/mod_sim_exp/trunk/