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[/] [mod_sim_exp/] [trunk/] - Rev 35

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Rev Log message Author Age Path
15 changed generic for register width from n to width for consistency JonasDC 4231d 00h /mod_sim_exp/trunk/
14 changed comments, file is now according to OC design rules JonasDC 4231d 01h /mod_sim_exp/trunk/
13 added some descriptive comments and added check for incorrect value's of width and block_width.
File is now according to OC design rules
JonasDC 4231d 01h /mod_sim_exp/trunk/
12 updated comments, file is now completely according to design rules JonasDC 4231d 01h /mod_sim_exp/trunk/
11 simulation output folder JonasDC 4231d 03h /mod_sim_exp/trunk/
10 changed signal input port names to correct name JonasDC 4231d 06h /mod_sim_exp/trunk/
9 added descriptive comments, and renamed input mux_result from cell_1b_adder to b for a more generic multipurpose code
also renamed output s from n_adder to r, to keep same signal names
JonasDC 4231d 06h /mod_sim_exp/trunk/
8 added descriptive comments JonasDC 4231d 08h /mod_sim_exp/trunk/
7 Modified the architecture, no longer uses Xilinx primitive, instead generic instantiation
added descriptive comments
JonasDC 4231d 08h /mod_sim_exp/trunk/
6 Modified the architecture, no longer uses Xilinx primitive, instead generic instantiation
added descriptive comments
JonasDC 4231d 09h /mod_sim_exp/trunk/

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