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[/] [mod_sim_exp/] [trunk/] - Rev 37

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Rev Log message Author Age Path
37 changed names of some generics of the multiplier.
moved the parameters for the core to the package of the core
testbench now uses this parameters to adapt to different bit widths

and new systolic pipeline now supports split or single pipeline		 JonasDC 4195d 11h /mod_sim_exp/trunk/
36 found bug in new pipeline structure, now working properly. (tested in sim)
mod_sim_exp_core uses new flexible pipeline as default.		 JonasDC 4196d 08h /mod_sim_exp/trunk/
35 new test values, 1st exponentiation gives error on result with new pipeline
commit for test purposes		 JonasDC 4196d 10h /mod_sim_exp/trunk/
34 operand memory now supports custom operand widths, the internal memory stays the fixed 1536 bit, but the bus width is now adjustable to any size below. JonasDC 4196d 11h /mod_sim_exp/trunk/
33 default pipeline changed to old version, there seems to be an occasional error with new version. JonasDC 4196d 14h /mod_sim_exp/trunk/
32 new systolic pipeline structure now has split pipeline support, tested and verified in simulation. the core now uses this pipeline by default. JonasDC 4196d 15h /mod_sim_exp/trunk/
31 put first cell logic of the pipeline in a separate design unit, tested and working JonasDC 4196d 20h /mod_sim_exp/trunk/
30 put last cell logic of the pipeline in a separate design unit, tested and working JonasDC 4196d 21h /mod_sim_exp/trunk/
29 added software for generation of test input for the tesbenches JonasDC 4197d 10h /mod_sim_exp/trunk/
28 updated makefile for new pipeline sources JonasDC 4197d 10h /mod_sim_exp/trunk/
27 test input values for multiplier_tb JonasDC 4197d 10h /mod_sim_exp/trunk/
26 testbench for only the montgommery multiplier JonasDC 4197d 10h /mod_sim_exp/trunk/
25 first version of new pipeline design. allows for more flexibility in nr of stages.
does not support split pipeline support yet. currently only works for single pipeline		 JonasDC 4197d 10h /mod_sim_exp/trunk/
24 changed names of top-level module to mod_sim_exp_core JonasDC 4200d 19h /mod_sim_exp/trunk/
23 added descriptive comments JonasDC 4200d 21h /mod_sim_exp/trunk/
22 updated the systolic pipeline with descriptive signal names and comments JonasDC 4203d 14h /mod_sim_exp/trunk/
21 changed x_i signal to xi JonasDC 4204d 22h /mod_sim_exp/trunk/
20 added comments, changed signal name of x_reg_i to x_reg.
File is now according to OC design rules		 JonasDC 4204d 22h /mod_sim_exp/trunk/
19 updated files with descriptive comments
changed signal names and removed redundant signals in stepping_logic		 JonasDC 4209d 17h /mod_sim_exp/trunk/
18 updated stages with comments and renamed some signals for consistency JonasDC 4210d 17h /mod_sim_exp/trunk/

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