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[/] [mod_sim_exp/] [trunk/] - Rev 39

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Rev Log message Author Age Path
19 updated files with descriptive comments
changed signal names and removed redundant signals in stepping_logic
JonasDC 4232d 13h /mod_sim_exp/trunk/
18 updated stages with comments and renamed some signals for consistency JonasDC 4233d 12h /mod_sim_exp/trunk/
17 updated files with descriptive comments and removed unnecessary signals in standard stage. Files are now according to OC design rules JonasDC 4233d 17h /mod_sim_exp/trunk/
16 package with modified generic parameter for register_n JonasDC 4234d 07h /mod_sim_exp/trunk/
15 changed generic for register width from n to width for consistency JonasDC 4234d 07h /mod_sim_exp/trunk/
14 changed comments, file is now according to OC design rules JonasDC 4234d 07h /mod_sim_exp/trunk/
13 added some descriptive comments and added check for incorrect value's of width and block_width.
File is now according to OC design rules
JonasDC 4234d 07h /mod_sim_exp/trunk/
12 updated comments, file is now completely according to design rules JonasDC 4234d 07h /mod_sim_exp/trunk/
11 simulation output folder JonasDC 4234d 09h /mod_sim_exp/trunk/
10 changed signal input port names to correct name JonasDC 4234d 12h /mod_sim_exp/trunk/

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