OpenCores
URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] - Rev 51

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
51 true dual port ram for xilinx JonasDC 3944d 00h /mod_sim_exp/trunk/
50 added folder for ram descriptions
added experimental simple dual port ram implementation for xilinx		 JonasDC 3944d 00h /mod_sim_exp/trunk/
47 added documentation for the IP core. JonasDC 4023d 23h /mod_sim_exp/trunk/
46 chance run_auto port or mod_sim_exp_core to exp_m JonasDC 4024d 00h /mod_sim_exp/trunk/
45 chance run_auto port or mod_sim_exp_core to exp_m JonasDC 4024d 00h /mod_sim_exp/trunk/
44 toplevel of the Modular Simultaneous Exponentiation IP core for the PLB interface JonasDC 4027d 17h /mod_sim_exp/trunk/
43 made the core parameters generics JonasDC 4027d 17h /mod_sim_exp/trunk/
42 corrected wrong library name for mod_sim_exp_pkg JonasDC 4034d 01h /mod_sim_exp/trunk/
41 removed deprecated files from version control JonasDC 4034d 01h /mod_sim_exp/trunk/
40 adjusted core instantiation to new core module name JonasDC 4042d 05h /mod_sim_exp/trunk/
39 changed files to remove warnings from synthesis
last cell logic is simplified because of redundant logic		 JonasDC 4042d 16h /mod_sim_exp/trunk/
38 deprecated design files because of new pipeline structure, will be removed shortly JonasDC 4042d 22h /mod_sim_exp/trunk/
37 changed names of some generics of the multiplier.
moved the parameters for the core to the package of the core
testbench now uses this parameters to adapt to different bit widths

and new systolic pipeline now supports split or single pipeline		 JonasDC 4046d 19h /mod_sim_exp/trunk/
36 found bug in new pipeline structure, now working properly. (tested in sim)
mod_sim_exp_core uses new flexible pipeline as default.		 JonasDC 4047d 15h /mod_sim_exp/trunk/
35 new test values, 1st exponentiation gives error on result with new pipeline
commit for test purposes		 JonasDC 4047d 17h /mod_sim_exp/trunk/
34 operand memory now supports custom operand widths, the internal memory stays the fixed 1536 bit, but the bus width is now adjustable to any size below. JonasDC 4047d 18h /mod_sim_exp/trunk/
33 default pipeline changed to old version, there seems to be an occasional error with new version. JonasDC 4047d 21h /mod_sim_exp/trunk/
32 new systolic pipeline structure now has split pipeline support, tested and verified in simulation. the core now uses this pipeline by default. JonasDC 4047d 22h /mod_sim_exp/trunk/
31 put first cell logic of the pipeline in a separate design unit, tested and working JonasDC 4048d 03h /mod_sim_exp/trunk/
30 put last cell logic of the pipeline in a separate design unit, tested and working JonasDC 4048d 04h /mod_sim_exp/trunk/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2023 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.