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[/] [mod_sim_exp/] [trunk/] - Rev 60

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Rev Log message Author Age Path
60 generic version of the fifo, not device specific anymore, uses dpram_generic
updated comments of RAM templates.
JonasDC 4026d 11h /mod_sim_exp/trunk/
59 added templates that correctly infer RAM, for dual port en true dual port RAM
added general functions file, (used in the two RAM templates)
JonasDC 4026d 11h /mod_sim_exp/trunk/
55 updated resource usage in comments JonasDC 4030d 11h /mod_sim_exp/trunk/
54 generic fifo design: correctrly inferred by xilinx and altera JonasDC 4030d 11h /mod_sim_exp/trunk/
53 correctly inferred ram for altera dual port ram JonasDC 4030d 18h /mod_sim_exp/trunk/
52 correct inferring of blockram, no additional resources. JonasDC 4030d 18h /mod_sim_exp/trunk/
51 true dual port ram for xilinx JonasDC 4030d 19h /mod_sim_exp/trunk/
50 added folder for ram descriptions
added experimental simple dual port ram implementation for xilinx
JonasDC 4030d 19h /mod_sim_exp/trunk/
47 added documentation for the IP core. JonasDC 4110d 18h /mod_sim_exp/trunk/
46 chance run_auto port or mod_sim_exp_core to exp_m JonasDC 4110d 19h /mod_sim_exp/trunk/
45 chance run_auto port or mod_sim_exp_core to exp_m JonasDC 4110d 19h /mod_sim_exp/trunk/
44 toplevel of the Modular Simultaneous Exponentiation IP core for the PLB interface JonasDC 4114d 12h /mod_sim_exp/trunk/
43 made the core parameters generics JonasDC 4114d 12h /mod_sim_exp/trunk/
42 corrected wrong library name for mod_sim_exp_pkg JonasDC 4120d 20h /mod_sim_exp/trunk/
41 removed deprecated files from version control JonasDC 4120d 20h /mod_sim_exp/trunk/
40 adjusted core instantiation to new core module name JonasDC 4129d 00h /mod_sim_exp/trunk/
39 changed files to remove warnings from synthesis
last cell logic is simplified because of redundant logic
JonasDC 4129d 11h /mod_sim_exp/trunk/
38 deprecated design files because of new pipeline structure, will be removed shortly JonasDC 4129d 17h /mod_sim_exp/trunk/
37 changed names of some generics of the multiplier.
moved the parameters for the core to the package of the core
testbench now uses this parameters to adapt to different bit widths

and new systolic pipeline now supports split or single pipeline
JonasDC 4133d 14h /mod_sim_exp/trunk/
36 found bug in new pipeline structure, now working properly. (tested in sim)
mod_sim_exp_core uses new flexible pipeline as default.
JonasDC 4134d 10h /mod_sim_exp/trunk/

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