OpenCores
URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] - Rev 62

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
62 not used anymore JonasDC 4077d 14h /mod_sim_exp/trunk/
61 updated comments, added optional altera constraint JonasDC 4077d 14h /mod_sim_exp/trunk/
60 generic version of the fifo, not device specific anymore, uses dpram_generic
updated comments of RAM templates.
JonasDC 4080d 05h /mod_sim_exp/trunk/
59 added templates that correctly infer RAM, for dual port en true dual port RAM
added general functions file, (used in the two RAM templates)
JonasDC 4080d 05h /mod_sim_exp/trunk/
55 updated resource usage in comments JonasDC 4084d 04h /mod_sim_exp/trunk/
54 generic fifo design: correctrly inferred by xilinx and altera JonasDC 4084d 05h /mod_sim_exp/trunk/
53 correctly inferred ram for altera dual port ram JonasDC 4084d 11h /mod_sim_exp/trunk/
52 correct inferring of blockram, no additional resources. JonasDC 4084d 12h /mod_sim_exp/trunk/
51 true dual port ram for xilinx JonasDC 4084d 12h /mod_sim_exp/trunk/
50 added folder for ram descriptions
added experimental simple dual port ram implementation for xilinx
JonasDC 4084d 12h /mod_sim_exp/trunk/
47 added documentation for the IP core. JonasDC 4164d 12h /mod_sim_exp/trunk/
46 chance run_auto port or mod_sim_exp_core to exp_m JonasDC 4164d 12h /mod_sim_exp/trunk/
45 chance run_auto port or mod_sim_exp_core to exp_m JonasDC 4164d 12h /mod_sim_exp/trunk/
44 toplevel of the Modular Simultaneous Exponentiation IP core for the PLB interface JonasDC 4168d 06h /mod_sim_exp/trunk/
43 made the core parameters generics JonasDC 4168d 06h /mod_sim_exp/trunk/
42 corrected wrong library name for mod_sim_exp_pkg JonasDC 4174d 14h /mod_sim_exp/trunk/
41 removed deprecated files from version control JonasDC 4174d 14h /mod_sim_exp/trunk/
40 adjusted core instantiation to new core module name JonasDC 4182d 18h /mod_sim_exp/trunk/
39 changed files to remove warnings from synthesis
last cell logic is simplified because of redundant logic
JonasDC 4183d 05h /mod_sim_exp/trunk/
38 deprecated design files because of new pipeline structure, will be removed shortly JonasDC 4183d 11h /mod_sim_exp/trunk/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.