Rev |
Log message |
Author |
Age |
Path |
63 |
now using a generic description of the ram for the memory. the core now should synthesize for al fpga's, no device specific code anymore. tested and synthesizes for altera and xilinx |
JonasDC |
4084d 19h |
/mod_sim_exp/trunk |
62 |
not used anymore |
JonasDC |
4084d 21h |
/mod_sim_exp/trunk |
61 |
updated comments, added optional altera constraint |
JonasDC |
4084d 21h |
/mod_sim_exp/trunk |
60 |
generic version of the fifo, not device specific anymore, uses dpram_generic
updated comments of RAM templates. |
JonasDC |
4087d 12h |
/mod_sim_exp/trunk |
59 |
added templates that correctly infer RAM, for dual port en true dual port RAM
added general functions file, (used in the two RAM templates) |
JonasDC |
4087d 12h |
/mod_sim_exp/trunk |
55 |
updated resource usage in comments |
JonasDC |
4091d 12h |
/mod_sim_exp/trunk |
54 |
generic fifo design: correctrly inferred by xilinx and altera |
JonasDC |
4091d 12h |
/mod_sim_exp/trunk |
53 |
correctly inferred ram for altera dual port ram |
JonasDC |
4091d 18h |
/mod_sim_exp/trunk |
52 |
correct inferring of blockram, no additional resources. |
JonasDC |
4091d 19h |
/mod_sim_exp/trunk |
51 |
true dual port ram for xilinx |
JonasDC |
4091d 19h |
/mod_sim_exp/trunk |
50 |
added folder for ram descriptions
added experimental simple dual port ram implementation for xilinx |
JonasDC |
4091d 19h |
/mod_sim_exp/trunk |
47 |
added documentation for the IP core. |
JonasDC |
4171d 19h |
/mod_sim_exp/trunk |
46 |
chance run_auto port or mod_sim_exp_core to exp_m |
JonasDC |
4171d 19h |
/mod_sim_exp/trunk |
45 |
chance run_auto port or mod_sim_exp_core to exp_m |
JonasDC |
4171d 19h |
/mod_sim_exp/trunk |
44 |
toplevel of the Modular Simultaneous Exponentiation IP core for the PLB interface |
JonasDC |
4175d 13h |
/mod_sim_exp/trunk |
43 |
made the core parameters generics |
JonasDC |
4175d 13h |
/mod_sim_exp/trunk |
42 |
corrected wrong library name for mod_sim_exp_pkg |
JonasDC |
4181d 21h |
/mod_sim_exp/trunk |
41 |
removed deprecated files from version control |
JonasDC |
4181d 21h |
/mod_sim_exp/trunk |
40 |
adjusted core instantiation to new core module name |
JonasDC |
4190d 01h |
/mod_sim_exp/trunk |
39 |
changed files to remove warnings from synthesis
last cell logic is simplified because of redundant logic |
JonasDC |
4190d 12h |
/mod_sim_exp/trunk |
38 |
deprecated design files because of new pipeline structure, will be removed shortly |
JonasDC |
4190d 18h |
/mod_sim_exp/trunk |
37 |
changed names of some generics of the multiplier.
moved the parameters for the core to the package of the core
testbench now uses this parameters to adapt to different bit widths
and new systolic pipeline now supports split or single pipeline |
JonasDC |
4194d 15h |
/mod_sim_exp/trunk |
36 |
found bug in new pipeline structure, now working properly. (tested in sim)
mod_sim_exp_core uses new flexible pipeline as default. |
JonasDC |
4195d 11h |
/mod_sim_exp/trunk |
35 |
new test values, 1st exponentiation gives error on result with new pipeline
commit for test purposes |
JonasDC |
4195d 13h |
/mod_sim_exp/trunk |
34 |
operand memory now supports custom operand widths, the internal memory stays the fixed 1536 bit, but the bus width is now adjustable to any size below. |
JonasDC |
4195d 14h |
/mod_sim_exp/trunk |
33 |
default pipeline changed to old version, there seems to be an occasional error with new version. |
JonasDC |
4195d 17h |
/mod_sim_exp/trunk |
32 |
new systolic pipeline structure now has split pipeline support, tested and verified in simulation. the core now uses this pipeline by default. |
JonasDC |
4195d 18h |
/mod_sim_exp/trunk |
31 |
put first cell logic of the pipeline in a separate design unit, tested and working |
JonasDC |
4195d 23h |
/mod_sim_exp/trunk |
30 |
put last cell logic of the pipeline in a separate design unit, tested and working |
JonasDC |
4196d 00h |
/mod_sim_exp/trunk |
29 |
added software for generation of test input for the tesbenches |
JonasDC |
4196d 13h |
/mod_sim_exp/trunk |