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[/] [mod_sim_exp/] [trunk/] - Rev 66

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Rev Log message Author Age Path
66 added asymmetric ram structures to support a more performant ramstyle.
defined for xilinx and altera, not tested with other tools.		 JonasDC 4070d 20h /mod_sim_exp/trunk/
65 updated plb interface, now modulus is selectable and, fifo depth is adjustable.
updated makefile with new sources and update component in package		 JonasDC 4078d 12h /mod_sim_exp/trunk/
64 added synthesis reports of xilinx and altera JonasDC 4078d 17h /mod_sim_exp/trunk/
63 now using a generic description of the ram for the memory. the core now should synthesize for al fpga's, no device specific code anymore. tested and synthesizes for altera and xilinx JonasDC 4078d 17h /mod_sim_exp/trunk/
62 not used anymore JonasDC 4078d 20h /mod_sim_exp/trunk/
61 updated comments, added optional altera constraint JonasDC 4078d 20h /mod_sim_exp/trunk/
60 generic version of the fifo, not device specific anymore, uses dpram_generic
updated comments of RAM templates.		 JonasDC 4081d 10h /mod_sim_exp/trunk/
59 added templates that correctly infer RAM, for dual port en true dual port RAM
added general functions file, (used in the two RAM templates)		 JonasDC 4081d 11h /mod_sim_exp/trunk/
55 updated resource usage in comments JonasDC 4085d 10h /mod_sim_exp/trunk/
54 generic fifo design: correctrly inferred by xilinx and altera JonasDC 4085d 11h /mod_sim_exp/trunk/
53 correctly inferred ram for altera dual port ram JonasDC 4085d 17h /mod_sim_exp/trunk/
52 correct inferring of blockram, no additional resources. JonasDC 4085d 18h /mod_sim_exp/trunk/
51 true dual port ram for xilinx JonasDC 4085d 18h /mod_sim_exp/trunk/
50 added folder for ram descriptions
added experimental simple dual port ram implementation for xilinx		 JonasDC 4085d 18h /mod_sim_exp/trunk/
47 added documentation for the IP core. JonasDC 4165d 18h /mod_sim_exp/trunk/
46 chance run_auto port or mod_sim_exp_core to exp_m JonasDC 4165d 18h /mod_sim_exp/trunk/
45 chance run_auto port or mod_sim_exp_core to exp_m JonasDC 4165d 18h /mod_sim_exp/trunk/
44 toplevel of the Modular Simultaneous Exponentiation IP core for the PLB interface JonasDC 4169d 12h /mod_sim_exp/trunk/
43 made the core parameters generics JonasDC 4169d 12h /mod_sim_exp/trunk/
42 corrected wrong library name for mod_sim_exp_pkg JonasDC 4175d 20h /mod_sim_exp/trunk/

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