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[/] [mod_sim_exp/] [trunk/] - Rev 72

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Rev	Log message	Author	Age	Path
72	deleted old resources	JonasDC	4909d 20h	/mod_sim_exp/trunk/
71	added synthesis report for altera and xilinx for the new ram. added coregen sources for xilinx for primitive RAM	JonasDC	4909d 20h	/mod_sim_exp/trunk/
70	updated testbench for use with new core parameters updated makefile, added new sources	JonasDC	4909d 20h	/mod_sim_exp/trunk/
69	big update, the mod_sim_exp core now has a selectable ram structure. a generic ram that should be usable in any fpga, a asymmetric ram that is usable for some devices of altera or xilinx and uses less resources.	JonasDC	4909d 20h	/mod_sim_exp/trunk/
67	added memory modules for modulus and operands for FPGA's that support asymmetric memory inferring.	JonasDC	4910d 00h	/mod_sim_exp/trunk/
66	added asymmetric ram structures to support a more performant ramstyle. defined for xilinx and altera, not tested with other tools.	JonasDC	4910d 00h	/mod_sim_exp/trunk/
65	updated plb interface, now modulus is selectable and, fifo depth is adjustable. updated makefile with new sources and update component in package	JonasDC	4917d 16h	/mod_sim_exp/trunk/
64	added synthesis reports of xilinx and altera	JonasDC	4917d 21h	/mod_sim_exp/trunk/
63	now using a generic description of the ram for the memory. the core now should synthesize for al fpga's, no device specific code anymore. tested and synthesizes for altera and xilinx	JonasDC	4917d 21h	/mod_sim_exp/trunk/
62	not used anymore	JonasDC	4918d 00h	/mod_sim_exp/trunk/
61	updated comments, added optional altera constraint	JonasDC	4918d 00h	/mod_sim_exp/trunk/
60	generic version of the fifo, not device specific anymore, uses dpram_generic updated comments of RAM templates.	JonasDC	4920d 14h	/mod_sim_exp/trunk/
59	added templates that correctly infer RAM, for dual port en true dual port RAM added general functions file, (used in the two RAM templates)	JonasDC	4920d 15h	/mod_sim_exp/trunk/
55	updated resource usage in comments	JonasDC	4924d 14h	/mod_sim_exp/trunk/
54	generic fifo design: correctrly inferred by xilinx and altera	JonasDC	4924d 14h	/mod_sim_exp/trunk/
53	correctly inferred ram for altera dual port ram	JonasDC	4924d 21h	/mod_sim_exp/trunk/
52	correct inferring of blockram, no additional resources.	JonasDC	4924d 21h	/mod_sim_exp/trunk/
51	true dual port ram for xilinx	JonasDC	4924d 22h	/mod_sim_exp/trunk/
50	added folder for ram descriptions added experimental simple dual port ram implementation for xilinx	JonasDC	4924d 22h	/mod_sim_exp/trunk/
47	added documentation for the IP core.	JonasDC	5004d 22h	/mod_sim_exp/trunk/

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[/] [mod_sim_exp/] [trunk/] - Rev 72

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