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[/] [mod_sim_exp/] [trunk/] - Rev 85

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Rev Log message Author Age Path
85 changed so that reset now also affects slave register JonasDC 4011d 23h /mod_sim_exp/trunk/
84 AXI-Lite interface updated, now tested and verified on Xilinx FPGA
renamed C_DEVICE parameter, because of conflicts with restricted parameter in xilinx XPS
JonasDC 4013d 07h /mod_sim_exp/trunk/
83 now using values from mod_sim_exp_pkg instead of direct entity JonasDC 4015d 08h /mod_sim_exp/trunk/
82 added first version of axi-lite interface and testbench for basic axi-lite operations, now under test JonasDC 4032d 04h /mod_sim_exp/trunk/
81 updated files, now using the components of the mod_sim_exp_pkg instead of direct entity declaration JonasDC 4032d 04h /mod_sim_exp/trunk/
78 updated documentation with new RAM style information JonasDC 4041d 22h /mod_sim_exp/trunk/
77 found fault in code, now synthesizes normally JonasDC 4047d 20h /mod_sim_exp/trunk/
76 testbench update JonasDC 4050d 07h /mod_sim_exp/trunk/
75 made rw_address a vector of a fixed width JonasDC 4050d 07h /mod_sim_exp/trunk/
74 removed C_NR_OP and C_NR_M from the generic of mod_sim_exp_core and made them contstants, because currently no other values than 4 an 2 resp. are supported/can be implemented. JonasDC 4053d 03h /mod_sim_exp/trunk/
73 updated plb interface, mem_style and device generics added JonasDC 4054d 02h /mod_sim_exp/trunk/
72 deleted old resources JonasDC 4055d 02h /mod_sim_exp/trunk/
71 added synthesis report for altera and xilinx for the new ram.
added coregen sources for xilinx for primitive RAM
JonasDC 4055d 02h /mod_sim_exp/trunk/
70 updated testbench for use with new core parameters
updated makefile, added new sources
JonasDC 4055d 02h /mod_sim_exp/trunk/
69 big update, the mod_sim_exp core now has a selectable ram structure. a generic ram that should be usable in any fpga, a asymmetric ram that is usable for some devices of altera or xilinx and uses less resources. JonasDC 4055d 02h /mod_sim_exp/trunk/
67 added memory modules for modulus and operands for FPGA's that support asymmetric memory inferring. JonasDC 4055d 05h /mod_sim_exp/trunk/
66 added asymmetric ram structures to support a more performant ramstyle.
defined for xilinx and altera, not tested with other tools.
JonasDC 4055d 05h /mod_sim_exp/trunk/
65 updated plb interface, now modulus is selectable and, fifo depth is adjustable.
updated makefile with new sources and update component in package
JonasDC 4062d 21h /mod_sim_exp/trunk/
64 added synthesis reports of xilinx and altera JonasDC 4063d 03h /mod_sim_exp/trunk/
63 now using a generic description of the ram for the memory. the core now should synthesize for al fpga's, no device specific code anymore. tested and synthesizes for altera and xilinx JonasDC 4063d 03h /mod_sim_exp/trunk/

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