| Rev |
Log message |
Author |
Age |
Path |
| 97 |
changes in makefile, and fifo's are now also in mod_sim_exp library |
JonasDC |
3937d 18h |
/mod_sim_exp/trunk/ |
| 96 |
minor makefile update |
JonasDC |
3938d 19h |
/mod_sim_exp/trunk/ |
| 95 |
new control logic for the core, allow for greater frequencies for the multiplier.
changes:
- autorun_cntrl: the bit selection for the exponents is now implemented with a shift register in stead of a mux. credits to Geoffrey Ottoy for new design structure.
- mont_cntrl: gave the databus from and to the RAM more time to settle. data now has 3 clocks to get to its destination. |
JonasDC |
3938d 19h |
/mod_sim_exp/trunk/ |
| 94 |
BIG update: core now supports different clock speed for the multiplier core, so more performance is posible. currently this version is working in simulation and is being tested on hardware. Changes in this update include:
- changed RAM and memory to support different clocks
- new FIFO that supports dual clock (slightly modified version of generic_fifo's on OpenCores.org)
- parameter C_FIFO_DEPTH is now replace by C_FIFO_AW (address width of the fifo pointers)
- added logic for control signals to cross from one clock domain to another
- updated testbenches and interfaces accordingly
- added log of synthesis of the 2 new fifo's for Xilinx |
JonasDC |
3951d 15h |
/mod_sim_exp/trunk/ |
| 92 |
updated documentation with minor interrupt changes of AXI interface |
JonasDC |
3953d 20h |
/mod_sim_exp/trunk/ |
| 91 |
changed interrupt structure of AXI4-Lite interface. Now the interrupt has to be acknowledged by clearing the appropriate interrupt source flag in the control register. |
JonasDC |
3955d 23h |
/mod_sim_exp/trunk/ |
| 90 |
reverted changes from previous revision, updated AXI version with testbench |
JonasDC |
3957d 13h |
/mod_sim_exp/trunk/ |
| 89 |
updated vhdl files so now different clock frequencies are posible for the core and bus interface. |
JonasDC |
4021d 12h |
/mod_sim_exp/trunk/ |
| 88 |
small update on documentation, changed fault in axi control_reg |
JonasDC |
4027d 13h |
/mod_sim_exp/trunk/ |
| 87 |
updated documentation to version 1.4
core now supports the AXI4-Lite bus |
JonasDC |
4027d 13h |
/mod_sim_exp/trunk/ |
| 86 |
update on previous |
JonasDC |
4027d 13h |
/mod_sim_exp/trunk/ |
| 85 |
changed so that reset now also affects slave register |
JonasDC |
4027d 13h |
/mod_sim_exp/trunk/ |
| 84 |
AXI-Lite interface updated, now tested and verified on Xilinx FPGA
renamed C_DEVICE parameter, because of conflicts with restricted parameter in xilinx XPS |
JonasDC |
4028d 22h |
/mod_sim_exp/trunk/ |
| 83 |
now using values from mod_sim_exp_pkg instead of direct entity |
JonasDC |
4030d 23h |
/mod_sim_exp/trunk/ |
| 82 |
added first version of axi-lite interface and testbench for basic axi-lite operations, now under test |
JonasDC |
4047d 19h |
/mod_sim_exp/trunk/ |
| 81 |
updated files, now using the components of the mod_sim_exp_pkg instead of direct entity declaration |
JonasDC |
4047d 19h |
/mod_sim_exp/trunk/ |
| 78 |
updated documentation with new RAM style information |
JonasDC |
4057d 13h |
/mod_sim_exp/trunk/ |
| 77 |
found fault in code, now synthesizes normally |
JonasDC |
4063d 10h |
/mod_sim_exp/trunk/ |
| 76 |
testbench update |
JonasDC |
4065d 21h |
/mod_sim_exp/trunk/ |
| 75 |
made rw_address a vector of a fixed width |
JonasDC |
4065d 21h |
/mod_sim_exp/trunk/ |
| 74 |
removed C_NR_OP and C_NR_M from the generic of mod_sim_exp_core and made them contstants, because currently no other values than 4 an 2 resp. are supported/can be implemented. |
JonasDC |
4068d 17h |
/mod_sim_exp/trunk/ |
| 73 |
updated plb interface, mem_style and device generics added |
JonasDC |
4069d 16h |
/mod_sim_exp/trunk/ |
| 72 |
deleted old resources |
JonasDC |
4070d 17h |
/mod_sim_exp/trunk/ |
| 71 |
added synthesis report for altera and xilinx for the new ram.
added coregen sources for xilinx for primitive RAM |
JonasDC |
4070d 17h |
/mod_sim_exp/trunk/ |
| 70 |
updated testbench for use with new core parameters
updated makefile, added new sources |
JonasDC |
4070d 17h |
/mod_sim_exp/trunk/ |
| 69 |
big update, the mod_sim_exp core now has a selectable ram structure. a generic ram that should be usable in any fpga, a asymmetric ram that is usable for some devices of altera or xilinx and uses less resources. |
JonasDC |
4070d 17h |
/mod_sim_exp/trunk/ |
| 67 |
added memory modules for modulus and operands for FPGA's that support asymmetric memory inferring. |
JonasDC |
4070d 20h |
/mod_sim_exp/trunk/ |
| 66 |
added asymmetric ram structures to support a more performant ramstyle.
defined for xilinx and altera, not tested with other tools. |
JonasDC |
4070d 20h |
/mod_sim_exp/trunk/ |
| 65 |
updated plb interface, now modulus is selectable and, fifo depth is adjustable.
updated makefile with new sources and update component in package |
JonasDC |
4078d 12h |
/mod_sim_exp/trunk/ |
| 64 |
added synthesis reports of xilinx and altera |
JonasDC |
4078d 17h |
/mod_sim_exp/trunk/ |
