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[/] [mod_sim_exp/] [trunk/] [bench/] - Rev 66

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Rev Log message Author Age Path
46 chance run_auto port or mod_sim_exp_core to exp_m JonasDC 4135d 06h /mod_sim_exp/trunk/bench/
43 made the core parameters generics JonasDC 4139d 00h /mod_sim_exp/trunk/bench/
37 changed names of some generics of the multiplier.
moved the parameters for the core to the package of the core
testbench now uses this parameters to adapt to different bit widths

and new systolic pipeline now supports split or single pipeline
JonasDC 4158d 01h /mod_sim_exp/trunk/bench/
26 testbench for only the montgommery multiplier JonasDC 4160d 00h /mod_sim_exp/trunk/bench/
24 changed names of top-level module to mod_sim_exp_core JonasDC 4163d 09h /mod_sim_exp/trunk/bench/
3 updated vhdl sources with new header according to OC design rules and formated code
added makefile and simulation input file for testbench simulation
JonasDC 4175d 01h /mod_sim_exp/trunk/bench/
2 First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules.. JonasDC 4179d 07h /mod_sim_exp/trunk/bench/

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