OpenCores
URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [bench/] - Rev 92

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
90 reverted changes from previous revision, updated AXI version with testbench JonasDC 3955d 18h /mod_sim_exp/trunk/bench/
84 AXI-Lite interface updated, now tested and verified on Xilinx FPGA
renamed C_DEVICE parameter, because of conflicts with restricted parameter in xilinx XPS		 JonasDC 4027d 02h /mod_sim_exp/trunk/bench/
82 added first version of axi-lite interface and testbench for basic axi-lite operations, now under test JonasDC 4045d 23h /mod_sim_exp/trunk/bench/
76 testbench update JonasDC 4064d 02h /mod_sim_exp/trunk/bench/
70 updated testbench for use with new core parameters
updated makefile, added new sources		 JonasDC 4068d 21h /mod_sim_exp/trunk/bench/
46 chance run_auto port or mod_sim_exp_core to exp_m JonasDC 4163d 23h /mod_sim_exp/trunk/bench/
43 made the core parameters generics JonasDC 4167d 16h /mod_sim_exp/trunk/bench/
37 changed names of some generics of the multiplier.
moved the parameters for the core to the package of the core
testbench now uses this parameters to adapt to different bit widths

and new systolic pipeline now supports split or single pipeline		 JonasDC 4186d 18h /mod_sim_exp/trunk/bench/
26 testbench for only the montgommery multiplier JonasDC 4188d 17h /mod_sim_exp/trunk/bench/
24 changed names of top-level module to mod_sim_exp_core JonasDC 4192d 02h /mod_sim_exp/trunk/bench/
3 updated vhdl sources with new header according to OC design rules and formated code
added makefile and simulation input file for testbench simulation		 JonasDC 4203d 17h /mod_sim_exp/trunk/bench/
2 First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules.. JonasDC 4207d 23h /mod_sim_exp/trunk/bench/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.