OpenCores
URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [bench/] [vhdl/] - Rev 94

Rev

Filtering Options

Clear current filter

Rev Log message Author Age Path
94 BIG update: core now supports different clock speed for the multiplier core, so more performance is posible. currently this version is working in simulation and is being tested on hardware. Changes in this update include:
- changed RAM and memory to support different clocks
- new FIFO that supports dual clock (slightly modified version of generic_fifo's on OpenCores.org)
- parameter C_FIFO_DEPTH is now replace by C_FIFO_AW (address width of the fifo pointers)
- added logic for control signals to cross from one clock domain to another
- updated testbenches and interfaces accordingly
- added log of synthesis of the 2 new fifo's for Xilinx
JonasDC 4008d 10h /mod_sim_exp/trunk/bench/vhdl/
90 reverted changes from previous revision, updated AXI version with testbench JonasDC 4014d 09h /mod_sim_exp/trunk/bench/vhdl/
84 AXI-Lite interface updated, now tested and verified on Xilinx FPGA
renamed C_DEVICE parameter, because of conflicts with restricted parameter in xilinx XPS
JonasDC 4085d 17h /mod_sim_exp/trunk/bench/vhdl/
82 added first version of axi-lite interface and testbench for basic axi-lite operations, now under test JonasDC 4104d 14h /mod_sim_exp/trunk/bench/vhdl/
76 testbench update JonasDC 4122d 16h /mod_sim_exp/trunk/bench/vhdl/
70 updated testbench for use with new core parameters
updated makefile, added new sources
JonasDC 4127d 12h /mod_sim_exp/trunk/bench/vhdl/
46 chance run_auto port or mod_sim_exp_core to exp_m JonasDC 4222d 13h /mod_sim_exp/trunk/bench/vhdl/
43 made the core parameters generics JonasDC 4226d 07h /mod_sim_exp/trunk/bench/vhdl/
37 changed names of some generics of the multiplier.
moved the parameters for the core to the package of the core
testbench now uses this parameters to adapt to different bit widths

and new systolic pipeline now supports split or single pipeline
JonasDC 4245d 08h /mod_sim_exp/trunk/bench/vhdl/
26 testbench for only the montgommery multiplier JonasDC 4247d 07h /mod_sim_exp/trunk/bench/vhdl/
24 changed names of top-level module to mod_sim_exp_core JonasDC 4250d 16h /mod_sim_exp/trunk/bench/vhdl/
3 updated vhdl sources with new header according to OC design rules and formated code
added makefile and simulation input file for testbench simulation
JonasDC 4262d 08h /mod_sim_exp/trunk/bench/vhdl/
2 First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules.. JonasDC 4266d 14h /mod_sim_exp/trunk/bench/vhdl/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.