URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [bench/] [vhdl/] [mod_sim_exp_core_tb.vhd] - Rev 67

Rev	Log message	Author	Age	Path
46	chance run_auto port or mod_sim_exp_core to exp_m	JonasDC	4184d 11h	/mod_sim_exp/trunk/bench/vhdl/mod_sim_exp_core_tb.vhd
43	made the core parameters generics	JonasDC	4188d 04h	/mod_sim_exp/trunk/bench/vhdl/mod_sim_exp_core_tb.vhd
37	changed names of some generics of the multiplier. moved the parameters for the core to the package of the core testbench now uses this parameters to adapt to different bit widths and new systolic pipeline now supports split or single pipeline	JonasDC	4207d 06h	/mod_sim_exp/trunk/bench/vhdl/mod_sim_exp_core_tb.vhd
24	changed names of top-level module to mod_sim_exp_core	JonasDC	4212d 14h	/mod_sim_exp/trunk/bench/vhdl/mod_sim_exp_core_tb.vhd
3	updated vhdl sources with new header according to OC design rules and formated code added makefile and simulation input file for testbench simulation	JonasDC	4224d 05h	/mod_sim_exp/trunk/bench/vhdl/tb_multiplier_core.vhd
2	First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules..	JonasDC	4228d 11h	/mod_sim_exp/trunk/bench/vhdl/tb_multiplier_core.vhd