URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [bench/] [vhdl/] [mod_sim_exp_core_tb.vhd] - Rev 70

Rev	Log message	Author	Age	Path
70	updated testbench for use with new core parameters updated makefile, added new sources	JonasDC	4849d 03h	/mod_sim_exp/trunk/bench/vhdl/mod_sim_exp_core_tb.vhd
46	chance run_auto port or mod_sim_exp_core to exp_m	JonasDC	4944d 04h	/mod_sim_exp/trunk/bench/vhdl/mod_sim_exp_core_tb.vhd
43	made the core parameters generics	JonasDC	4947d 21h	/mod_sim_exp/trunk/bench/vhdl/mod_sim_exp_core_tb.vhd
37	changed names of some generics of the multiplier. moved the parameters for the core to the package of the core testbench now uses this parameters to adapt to different bit widths and new systolic pipeline now supports split or single pipeline	JonasDC	4966d 23h	/mod_sim_exp/trunk/bench/vhdl/mod_sim_exp_core_tb.vhd
24	changed names of top-level module to mod_sim_exp_core	JonasDC	4972d 07h	/mod_sim_exp/trunk/bench/vhdl/mod_sim_exp_core_tb.vhd
3	updated vhdl sources with new header according to OC design rules and formated code added makefile and simulation input file for testbench simulation	JonasDC	4983d 23h	/mod_sim_exp/trunk/bench/vhdl/tb_multiplier_core.vhd
2	First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules..	JonasDC	4988d 05h	/mod_sim_exp/trunk/bench/vhdl/tb_multiplier_core.vhd