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[/] [mod_sim_exp/] [trunk/] [bench/] [vhdl/] [mod_sim_exp_core_tb.vhd] - Rev 84

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84 AXI-Lite interface updated, now tested and verified on Xilinx FPGA
renamed C_DEVICE parameter, because of conflicts with restricted parameter in xilinx XPS
JonasDC 3411d 00h /mod_sim_exp/trunk/bench/vhdl/mod_sim_exp_core_tb.vhd
76 testbench update JonasDC 3447d 23h /mod_sim_exp/trunk/bench/vhdl/mod_sim_exp_core_tb.vhd
70 updated testbench for use with new core parameters
updated makefile, added new sources
JonasDC 3452d 19h /mod_sim_exp/trunk/bench/vhdl/mod_sim_exp_core_tb.vhd
46 chance run_auto port or mod_sim_exp_core to exp_m JonasDC 3547d 20h /mod_sim_exp/trunk/bench/vhdl/mod_sim_exp_core_tb.vhd
43 made the core parameters generics JonasDC 3551d 14h /mod_sim_exp/trunk/bench/vhdl/mod_sim_exp_core_tb.vhd
37 changed names of some generics of the multiplier.
moved the parameters for the core to the package of the core
testbench now uses this parameters to adapt to different bit widths

and new systolic pipeline now supports split or single pipeline
JonasDC 3570d 15h /mod_sim_exp/trunk/bench/vhdl/mod_sim_exp_core_tb.vhd
24 changed names of top-level module to mod_sim_exp_core JonasDC 3575d 23h /mod_sim_exp/trunk/bench/vhdl/mod_sim_exp_core_tb.vhd
3 updated vhdl sources with new header according to OC design rules and formated code
added makefile and simulation input file for testbench simulation
JonasDC 3587d 15h /mod_sim_exp/trunk/bench/vhdl/tb_multiplier_core.vhd
2 First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules.. JonasDC 3591d 21h /mod_sim_exp/trunk/bench/vhdl/tb_multiplier_core.vhd

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