Rev |
Log message |
Author |
Age |
Path |
97 |
changes in makefile, and fifo's are now also in mod_sim_exp library |
JonasDC |
3969d 16h |
/mod_sim_exp/trunk/rtl/ |
95 |
new control logic for the core, allow for greater frequencies for the multiplier.
changes:
- autorun_cntrl: the bit selection for the exponents is now implemented with a shift register in stead of a mux. credits to Geoffrey Ottoy for new design structure.
- mont_cntrl: gave the databus from and to the RAM more time to settle. data now has 3 clocks to get to its destination. |
JonasDC |
3970d 17h |
/mod_sim_exp/trunk/rtl/ |
94 |
BIG update: core now supports different clock speed for the multiplier core, so more performance is posible. currently this version is working in simulation and is being tested on hardware. Changes in this update include:
- changed RAM and memory to support different clocks
- new FIFO that supports dual clock (slightly modified version of generic_fifo's on OpenCores.org)
- parameter C_FIFO_DEPTH is now replace by C_FIFO_AW (address width of the fifo pointers)
- added logic for control signals to cross from one clock domain to another
- updated testbenches and interfaces accordingly
- added log of synthesis of the 2 new fifo's for Xilinx |
JonasDC |
3983d 13h |
/mod_sim_exp/trunk/rtl/ |
91 |
changed interrupt structure of AXI4-Lite interface. Now the interrupt has to be acknowledged by clearing the appropriate interrupt source flag in the control register. |
JonasDC |
3987d 21h |
/mod_sim_exp/trunk/rtl/ |
90 |
reverted changes from previous revision, updated AXI version with testbench |
JonasDC |
3989d 11h |
/mod_sim_exp/trunk/rtl/ |
89 |
updated vhdl files so now different clock frequencies are posible for the core and bus interface. |
JonasDC |
4053d 10h |
/mod_sim_exp/trunk/rtl/ |
86 |
update on previous |
JonasDC |
4059d 11h |
/mod_sim_exp/trunk/rtl/ |
85 |
changed so that reset now also affects slave register |
JonasDC |
4059d 11h |
/mod_sim_exp/trunk/rtl/ |
84 |
AXI-Lite interface updated, now tested and verified on Xilinx FPGA
renamed C_DEVICE parameter, because of conflicts with restricted parameter in xilinx XPS |
JonasDC |
4060d 20h |
/mod_sim_exp/trunk/rtl/ |
83 |
now using values from mod_sim_exp_pkg instead of direct entity |
JonasDC |
4062d 21h |
/mod_sim_exp/trunk/rtl/ |
82 |
added first version of axi-lite interface and testbench for basic axi-lite operations, now under test |
JonasDC |
4079d 17h |
/mod_sim_exp/trunk/rtl/ |
81 |
updated files, now using the components of the mod_sim_exp_pkg instead of direct entity declaration |
JonasDC |
4079d 17h |
/mod_sim_exp/trunk/rtl/ |
77 |
found fault in code, now synthesizes normally |
JonasDC |
4095d 08h |
/mod_sim_exp/trunk/rtl/ |
75 |
made rw_address a vector of a fixed width |
JonasDC |
4097d 19h |
/mod_sim_exp/trunk/rtl/ |
74 |
removed C_NR_OP and C_NR_M from the generic of mod_sim_exp_core and made them contstants, because currently no other values than 4 an 2 resp. are supported/can be implemented. |
JonasDC |
4100d 15h |
/mod_sim_exp/trunk/rtl/ |
73 |
updated plb interface, mem_style and device generics added |
JonasDC |
4101d 14h |
/mod_sim_exp/trunk/rtl/ |
69 |
big update, the mod_sim_exp core now has a selectable ram structure. a generic ram that should be usable in any fpga, a asymmetric ram that is usable for some devices of altera or xilinx and uses less resources. |
JonasDC |
4102d 15h |
/mod_sim_exp/trunk/rtl/ |
67 |
added memory modules for modulus and operands for FPGA's that support asymmetric memory inferring. |
JonasDC |
4102d 18h |
/mod_sim_exp/trunk/rtl/ |
66 |
added asymmetric ram structures to support a more performant ramstyle.
defined for xilinx and altera, not tested with other tools. |
JonasDC |
4102d 18h |
/mod_sim_exp/trunk/rtl/ |
65 |
updated plb interface, now modulus is selectable and, fifo depth is adjustable.
updated makefile with new sources and update component in package |
JonasDC |
4110d 10h |
/mod_sim_exp/trunk/rtl/ |
63 |
now using a generic description of the ram for the memory. the core now should synthesize for al fpga's, no device specific code anymore. tested and synthesizes for altera and xilinx |
JonasDC |
4110d 15h |
/mod_sim_exp/trunk/rtl/ |
62 |
not used anymore |
JonasDC |
4110d 18h |
/mod_sim_exp/trunk/rtl/ |
61 |
updated comments, added optional altera constraint |
JonasDC |
4110d 18h |
/mod_sim_exp/trunk/rtl/ |
60 |
generic version of the fifo, not device specific anymore, uses dpram_generic
updated comments of RAM templates. |
JonasDC |
4113d 08h |
/mod_sim_exp/trunk/rtl/ |
59 |
added templates that correctly infer RAM, for dual port en true dual port RAM
added general functions file, (used in the two RAM templates) |
JonasDC |
4113d 09h |
/mod_sim_exp/trunk/rtl/ |
55 |
updated resource usage in comments |
JonasDC |
4117d 08h |
/mod_sim_exp/trunk/rtl/ |
54 |
generic fifo design: correctrly inferred by xilinx and altera |
JonasDC |
4117d 08h |
/mod_sim_exp/trunk/rtl/ |
53 |
correctly inferred ram for altera dual port ram |
JonasDC |
4117d 15h |
/mod_sim_exp/trunk/rtl/ |
52 |
correct inferring of blockram, no additional resources. |
JonasDC |
4117d 15h |
/mod_sim_exp/trunk/rtl/ |
51 |
true dual port ram for xilinx |
JonasDC |
4117d 16h |
/mod_sim_exp/trunk/rtl/ |