OpenCores
URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [rtl/] - Rev 26

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
25 first version of new pipeline design. allows for more flexibility in nr of stages.
does not support split pipeline support yet. currently only works for single pipeline
JonasDC 3741d 07h /mod_sim_exp/trunk/rtl/
24 changed names of top-level module to mod_sim_exp_core JonasDC 3744d 16h /mod_sim_exp/trunk/rtl/
23 added descriptive comments JonasDC 3744d 17h /mod_sim_exp/trunk/rtl/
22 updated the systolic pipeline with descriptive signal names and comments JonasDC 3747d 11h /mod_sim_exp/trunk/rtl/
21 changed x_i signal to xi JonasDC 3748d 19h /mod_sim_exp/trunk/rtl/
20 added comments, changed signal name of x_reg_i to x_reg.
File is now according to OC design rules
JonasDC 3748d 19h /mod_sim_exp/trunk/rtl/
19 updated files with descriptive comments
changed signal names and removed redundant signals in stepping_logic
JonasDC 3753d 14h /mod_sim_exp/trunk/rtl/
18 updated stages with comments and renamed some signals for consistency JonasDC 3754d 14h /mod_sim_exp/trunk/rtl/
17 updated files with descriptive comments and removed unnecessary signals in standard stage. Files are now according to OC design rules JonasDC 3754d 19h /mod_sim_exp/trunk/rtl/
16 package with modified generic parameter for register_n JonasDC 3755d 08h /mod_sim_exp/trunk/rtl/
15 changed generic for register width from n to width for consistency JonasDC 3755d 08h /mod_sim_exp/trunk/rtl/
14 changed comments, file is now according to OC design rules JonasDC 3755d 08h /mod_sim_exp/trunk/rtl/
13 added some descriptive comments and added check for incorrect value's of width and block_width.
File is now according to OC design rules
JonasDC 3755d 08h /mod_sim_exp/trunk/rtl/
12 updated comments, file is now completely according to design rules JonasDC 3755d 08h /mod_sim_exp/trunk/rtl/
10 changed signal input port names to correct name JonasDC 3755d 13h /mod_sim_exp/trunk/rtl/
9 added descriptive comments, and renamed input mux_result from cell_1b_adder to b for a more generic multipurpose code
also renamed output s from n_adder to r, to keep same signal names
JonasDC 3755d 13h /mod_sim_exp/trunk/rtl/
8 added descriptive comments JonasDC 3755d 15h /mod_sim_exp/trunk/rtl/
7 Modified the architecture, no longer uses Xilinx primitive, instead generic instantiation
added descriptive comments
JonasDC 3755d 16h /mod_sim_exp/trunk/rtl/
6 Modified the architecture, no longer uses Xilinx primitive, instead generic instantiation
added descriptive comments
JonasDC 3755d 16h /mod_sim_exp/trunk/rtl/
4 Modified the architecture, no longer uses Xilinx primitive, instead generic instantiation
added descriptive comments
JonasDC 3755d 18h /mod_sim_exp/trunk/rtl/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2023 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.