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[/] [mod_sim_exp/] [trunk/] [rtl/] - Rev 34

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Rev	Log message	Author	Age	Path
34	operand memory now supports custom operand widths, the internal memory stays the fixed 1536 bit, but the bus width is now adjustable to any size below.	JonasDC	4208d 14h	/mod_sim_exp/trunk/rtl
33	default pipeline changed to old version, there seems to be an occasional error with new version.	JonasDC	4208d 17h	/mod_sim_exp/trunk/rtl
32	new systolic pipeline structure now has split pipeline support, tested and verified in simulation. the core now uses this pipeline by default.	JonasDC	4208d 18h	/mod_sim_exp/trunk/rtl
31	put first cell logic of the pipeline in a separate design unit, tested and working	JonasDC	4208d 23h	/mod_sim_exp/trunk/rtl
30	put last cell logic of the pipeline in a separate design unit, tested and working	JonasDC	4209d 00h	/mod_sim_exp/trunk/rtl
25	first version of new pipeline design. allows for more flexibility in nr of stages. does not support split pipeline support yet. currently only works for single pipeline	JonasDC	4209d 14h	/mod_sim_exp/trunk/rtl
24	changed names of top-level module to mod_sim_exp_core	JonasDC	4212d 23h	/mod_sim_exp/trunk/rtl
23	added descriptive comments	JonasDC	4213d 00h	/mod_sim_exp/trunk/rtl
22	updated the systolic pipeline with descriptive signal names and comments	JonasDC	4215d 17h	/mod_sim_exp/trunk/rtl
21	changed x_i signal to xi	JonasDC	4217d 01h	/mod_sim_exp/trunk/rtl
20	added comments, changed signal name of x_reg_i to x_reg. File is now according to OC design rules	JonasDC	4217d 01h	/mod_sim_exp/trunk/rtl
19	updated files with descriptive comments changed signal names and removed redundant signals in stepping_logic	JonasDC	4221d 20h	/mod_sim_exp/trunk/rtl
18	updated stages with comments and renamed some signals for consistency	JonasDC	4222d 20h	/mod_sim_exp/trunk/rtl
17	updated files with descriptive comments and removed unnecessary signals in standard stage. Files are now according to OC design rules	JonasDC	4223d 01h	/mod_sim_exp/trunk/rtl
16	package with modified generic parameter for register_n	JonasDC	4223d 14h	/mod_sim_exp/trunk/rtl
15	changed generic for register width from n to width for consistency	JonasDC	4223d 14h	/mod_sim_exp/trunk/rtl
14	changed comments, file is now according to OC design rules	JonasDC	4223d 15h	/mod_sim_exp/trunk/rtl
13	added some descriptive comments and added check for incorrect value's of width and block_width. File is now according to OC design rules	JonasDC	4223d 15h	/mod_sim_exp/trunk/rtl
12	updated comments, file is now completely according to design rules	JonasDC	4223d 15h	/mod_sim_exp/trunk/rtl
10	changed signal input port names to correct name	JonasDC	4223d 20h	/mod_sim_exp/trunk/rtl

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[/] [mod_sim_exp/] [trunk/] [rtl/] - Rev 34

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