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[/] [mod_sim_exp/] [trunk/] [rtl/] - Rev 40

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Rev Log message Author Age Path
15 changed generic for register width from n to width for consistency JonasDC 4259d 01h /mod_sim_exp/trunk/rtl/
14 changed comments, file is now according to OC design rules JonasDC 4259d 01h /mod_sim_exp/trunk/rtl/
13 added some descriptive comments and added check for incorrect value's of width and block_width.
File is now according to OC design rules
JonasDC 4259d 01h /mod_sim_exp/trunk/rtl/
12 updated comments, file is now completely according to design rules JonasDC 4259d 01h /mod_sim_exp/trunk/rtl/
10 changed signal input port names to correct name JonasDC 4259d 06h /mod_sim_exp/trunk/rtl/
9 added descriptive comments, and renamed input mux_result from cell_1b_adder to b for a more generic multipurpose code
also renamed output s from n_adder to r, to keep same signal names
JonasDC 4259d 06h /mod_sim_exp/trunk/rtl/
8 added descriptive comments JonasDC 4259d 09h /mod_sim_exp/trunk/rtl/
7 Modified the architecture, no longer uses Xilinx primitive, instead generic instantiation
added descriptive comments
JonasDC 4259d 09h /mod_sim_exp/trunk/rtl/
6 Modified the architecture, no longer uses Xilinx primitive, instead generic instantiation
added descriptive comments
JonasDC 4259d 09h /mod_sim_exp/trunk/rtl/
4 Modified the architecture, no longer uses Xilinx primitive, instead generic instantiation
added descriptive comments
JonasDC 4259d 11h /mod_sim_exp/trunk/rtl/

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