Rev |
Log message |
Author |
Age |
Path |
45 |
chance run_auto port or mod_sim_exp_core to exp_m |
JonasDC |
4178d 10h |
/mod_sim_exp/trunk/rtl/ |
44 |
toplevel of the Modular Simultaneous Exponentiation IP core for the PLB interface |
JonasDC |
4182d 04h |
/mod_sim_exp/trunk/rtl/ |
43 |
made the core parameters generics |
JonasDC |
4182d 04h |
/mod_sim_exp/trunk/rtl/ |
42 |
corrected wrong library name for mod_sim_exp_pkg |
JonasDC |
4188d 12h |
/mod_sim_exp/trunk/rtl/ |
41 |
removed deprecated files from version control |
JonasDC |
4188d 12h |
/mod_sim_exp/trunk/rtl/ |
40 |
adjusted core instantiation to new core module name |
JonasDC |
4196d 16h |
/mod_sim_exp/trunk/rtl/ |
39 |
changed files to remove warnings from synthesis
last cell logic is simplified because of redundant logic |
JonasDC |
4197d 03h |
/mod_sim_exp/trunk/rtl/ |
38 |
deprecated design files because of new pipeline structure, will be removed shortly |
JonasDC |
4197d 08h |
/mod_sim_exp/trunk/rtl/ |
37 |
changed names of some generics of the multiplier.
moved the parameters for the core to the package of the core
testbench now uses this parameters to adapt to different bit widths
and new systolic pipeline now supports split or single pipeline |
JonasDC |
4201d 05h |
/mod_sim_exp/trunk/rtl/ |
36 |
found bug in new pipeline structure, now working properly. (tested in sim)
mod_sim_exp_core uses new flexible pipeline as default. |
JonasDC |
4202d 02h |
/mod_sim_exp/trunk/rtl/ |
34 |
operand memory now supports custom operand widths, the internal memory stays the fixed 1536 bit, but the bus width is now adjustable to any size below. |
JonasDC |
4202d 05h |
/mod_sim_exp/trunk/rtl/ |
33 |
default pipeline changed to old version, there seems to be an occasional error with new version. |
JonasDC |
4202d 08h |
/mod_sim_exp/trunk/rtl/ |
32 |
new systolic pipeline structure now has split pipeline support, tested and verified in simulation. the core now uses this pipeline by default. |
JonasDC |
4202d 09h |
/mod_sim_exp/trunk/rtl/ |
31 |
put first cell logic of the pipeline in a separate design unit, tested and working |
JonasDC |
4202d 14h |
/mod_sim_exp/trunk/rtl/ |
30 |
put last cell logic of the pipeline in a separate design unit, tested and working |
JonasDC |
4202d 15h |
/mod_sim_exp/trunk/rtl/ |
25 |
first version of new pipeline design. allows for more flexibility in nr of stages.
does not support split pipeline support yet. currently only works for single pipeline |
JonasDC |
4203d 04h |
/mod_sim_exp/trunk/rtl/ |
24 |
changed names of top-level module to mod_sim_exp_core |
JonasDC |
4206d 13h |
/mod_sim_exp/trunk/rtl/ |
23 |
added descriptive comments |
JonasDC |
4206d 15h |
/mod_sim_exp/trunk/rtl/ |
22 |
updated the systolic pipeline with descriptive signal names and comments |
JonasDC |
4209d 08h |
/mod_sim_exp/trunk/rtl/ |
21 |
changed x_i signal to xi |
JonasDC |
4210d 16h |
/mod_sim_exp/trunk/rtl/ |
20 |
added comments, changed signal name of x_reg_i to x_reg.
File is now according to OC design rules |
JonasDC |
4210d 16h |
/mod_sim_exp/trunk/rtl/ |
19 |
updated files with descriptive comments
changed signal names and removed redundant signals in stepping_logic |
JonasDC |
4215d 11h |
/mod_sim_exp/trunk/rtl/ |
18 |
updated stages with comments and renamed some signals for consistency |
JonasDC |
4216d 11h |
/mod_sim_exp/trunk/rtl/ |
17 |
updated files with descriptive comments and removed unnecessary signals in standard stage. Files are now according to OC design rules |
JonasDC |
4216d 16h |
/mod_sim_exp/trunk/rtl/ |
16 |
package with modified generic parameter for register_n |
JonasDC |
4217d 05h |
/mod_sim_exp/trunk/rtl/ |
15 |
changed generic for register width from n to width for consistency |
JonasDC |
4217d 05h |
/mod_sim_exp/trunk/rtl/ |
14 |
changed comments, file is now according to OC design rules |
JonasDC |
4217d 05h |
/mod_sim_exp/trunk/rtl/ |
13 |
added some descriptive comments and added check for incorrect value's of width and block_width.
File is now according to OC design rules |
JonasDC |
4217d 05h |
/mod_sim_exp/trunk/rtl/ |
12 |
updated comments, file is now completely according to design rules |
JonasDC |
4217d 06h |
/mod_sim_exp/trunk/rtl/ |
10 |
changed signal input port names to correct name |
JonasDC |
4217d 10h |
/mod_sim_exp/trunk/rtl/ |