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[/] [mod_sim_exp/] [trunk/] [rtl/] - Rev 51

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Rev Log message Author Age Path
51 true dual port ram for xilinx JonasDC 4139d 03h /mod_sim_exp/trunk/rtl/
50 added folder for ram descriptions
added experimental simple dual port ram implementation for xilinx
JonasDC 4139d 03h /mod_sim_exp/trunk/rtl/
45 chance run_auto port or mod_sim_exp_core to exp_m JonasDC 4219d 03h /mod_sim_exp/trunk/rtl/
44 toplevel of the Modular Simultaneous Exponentiation IP core for the PLB interface JonasDC 4222d 21h /mod_sim_exp/trunk/rtl/
43 made the core parameters generics JonasDC 4222d 21h /mod_sim_exp/trunk/rtl/
42 corrected wrong library name for mod_sim_exp_pkg JonasDC 4229d 05h /mod_sim_exp/trunk/rtl/
41 removed deprecated files from version control JonasDC 4229d 05h /mod_sim_exp/trunk/rtl/
40 adjusted core instantiation to new core module name JonasDC 4237d 09h /mod_sim_exp/trunk/rtl/
39 changed files to remove warnings from synthesis
last cell logic is simplified because of redundant logic
JonasDC 4237d 20h /mod_sim_exp/trunk/rtl/
38 deprecated design files because of new pipeline structure, will be removed shortly JonasDC 4238d 02h /mod_sim_exp/trunk/rtl/
37 changed names of some generics of the multiplier.
moved the parameters for the core to the package of the core
testbench now uses this parameters to adapt to different bit widths

and new systolic pipeline now supports split or single pipeline
JonasDC 4241d 23h /mod_sim_exp/trunk/rtl/
36 found bug in new pipeline structure, now working properly. (tested in sim)
mod_sim_exp_core uses new flexible pipeline as default.
JonasDC 4242d 19h /mod_sim_exp/trunk/rtl/
34 operand memory now supports custom operand widths, the internal memory stays the fixed 1536 bit, but the bus width is now adjustable to any size below. JonasDC 4242d 22h /mod_sim_exp/trunk/rtl/
33 default pipeline changed to old version, there seems to be an occasional error with new version. JonasDC 4243d 01h /mod_sim_exp/trunk/rtl/
32 new systolic pipeline structure now has split pipeline support, tested and verified in simulation. the core now uses this pipeline by default. JonasDC 4243d 02h /mod_sim_exp/trunk/rtl/
31 put first cell logic of the pipeline in a separate design unit, tested and working JonasDC 4243d 07h /mod_sim_exp/trunk/rtl/
30 put last cell logic of the pipeline in a separate design unit, tested and working JonasDC 4243d 08h /mod_sim_exp/trunk/rtl/
25 first version of new pipeline design. allows for more flexibility in nr of stages.
does not support split pipeline support yet. currently only works for single pipeline
JonasDC 4243d 22h /mod_sim_exp/trunk/rtl/
24 changed names of top-level module to mod_sim_exp_core JonasDC 4247d 07h /mod_sim_exp/trunk/rtl/
23 added descriptive comments JonasDC 4247d 08h /mod_sim_exp/trunk/rtl/

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