OpenCores
URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [rtl/] - Rev 67

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
67 added memory modules for modulus and operands for FPGA's that support asymmetric memory inferring. JonasDC 4457d 18h /mod_sim_exp/trunk/rtl/
66 added asymmetric ram structures to support a more performant ramstyle.
defined for xilinx and altera, not tested with other tools.		 JonasDC 4457d 18h /mod_sim_exp/trunk/rtl/
65 updated plb interface, now modulus is selectable and, fifo depth is adjustable.
updated makefile with new sources and update component in package		 JonasDC 4465d 10h /mod_sim_exp/trunk/rtl/
63 now using a generic description of the ram for the memory. the core now should synthesize for al fpga's, no device specific code anymore. tested and synthesizes for altera and xilinx JonasDC 4465d 16h /mod_sim_exp/trunk/rtl/
62 not used anymore JonasDC 4465d 18h /mod_sim_exp/trunk/rtl/
61 updated comments, added optional altera constraint JonasDC 4465d 18h /mod_sim_exp/trunk/rtl/
60 generic version of the fifo, not device specific anymore, uses dpram_generic
updated comments of RAM templates.		 JonasDC 4468d 09h /mod_sim_exp/trunk/rtl/
59 added templates that correctly infer RAM, for dual port en true dual port RAM
added general functions file, (used in the two RAM templates)		 JonasDC 4468d 09h /mod_sim_exp/trunk/rtl/
55 updated resource usage in comments JonasDC 4472d 09h /mod_sim_exp/trunk/rtl/
54 generic fifo design: correctrly inferred by xilinx and altera JonasDC 4472d 09h /mod_sim_exp/trunk/rtl/
53 correctly inferred ram for altera dual port ram JonasDC 4472d 15h /mod_sim_exp/trunk/rtl/
52 correct inferring of blockram, no additional resources. JonasDC 4472d 16h /mod_sim_exp/trunk/rtl/
51 true dual port ram for xilinx JonasDC 4472d 17h /mod_sim_exp/trunk/rtl/
50 added folder for ram descriptions
added experimental simple dual port ram implementation for xilinx		 JonasDC 4472d 17h /mod_sim_exp/trunk/rtl/
45 chance run_auto port or mod_sim_exp_core to exp_m JonasDC 4552d 17h /mod_sim_exp/trunk/rtl/
44 toplevel of the Modular Simultaneous Exponentiation IP core for the PLB interface JonasDC 4556d 10h /mod_sim_exp/trunk/rtl/
43 made the core parameters generics JonasDC 4556d 10h /mod_sim_exp/trunk/rtl/
42 corrected wrong library name for mod_sim_exp_pkg JonasDC 4562d 18h /mod_sim_exp/trunk/rtl/
41 removed deprecated files from version control JonasDC 4562d 18h /mod_sim_exp/trunk/rtl/
40 adjusted core instantiation to new core module name JonasDC 4570d 22h /mod_sim_exp/trunk/rtl/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2025 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.