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[/] [mod_sim_exp/] [trunk/] [rtl/] - Rev 68

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39 changed files to remove warnings from synthesis
last cell logic is simplified because of redundant logic		 JonasDC 4214d 14h /mod_sim_exp/trunk/rtl
38 deprecated design files because of new pipeline structure, will be removed shortly JonasDC 4214d 20h /mod_sim_exp/trunk/rtl
37 changed names of some generics of the multiplier.
moved the parameters for the core to the package of the core
testbench now uses this parameters to adapt to different bit widths

and new systolic pipeline now supports split or single pipeline		 JonasDC 4218d 17h /mod_sim_exp/trunk/rtl
36 found bug in new pipeline structure, now working properly. (tested in sim)
mod_sim_exp_core uses new flexible pipeline as default.		 JonasDC 4219d 13h /mod_sim_exp/trunk/rtl
34 operand memory now supports custom operand widths, the internal memory stays the fixed 1536 bit, but the bus width is now adjustable to any size below. JonasDC 4219d 17h /mod_sim_exp/trunk/rtl
33 default pipeline changed to old version, there seems to be an occasional error with new version. JonasDC 4219d 19h /mod_sim_exp/trunk/rtl
32 new systolic pipeline structure now has split pipeline support, tested and verified in simulation. the core now uses this pipeline by default. JonasDC 4219d 20h /mod_sim_exp/trunk/rtl
31 put first cell logic of the pipeline in a separate design unit, tested and working JonasDC 4220d 02h /mod_sim_exp/trunk/rtl
30 put last cell logic of the pipeline in a separate design unit, tested and working JonasDC 4220d 02h /mod_sim_exp/trunk/rtl
25 first version of new pipeline design. allows for more flexibility in nr of stages.
does not support split pipeline support yet. currently only works for single pipeline		 JonasDC 4220d 16h /mod_sim_exp/trunk/rtl

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