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[/] [mod_sim_exp/] [trunk/] [rtl/] - Rev 82

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Rev Log message Author Age Path
82 added first version of axi-lite interface and testbench for basic axi-lite operations, now under test JonasDC 4069d 01h /mod_sim_exp/trunk/rtl/
81 updated files, now using the components of the mod_sim_exp_pkg instead of direct entity declaration JonasDC 4069d 01h /mod_sim_exp/trunk/rtl/
77 found fault in code, now synthesizes normally JonasDC 4084d 17h /mod_sim_exp/trunk/rtl/
75 made rw_address a vector of a fixed width JonasDC 4087d 04h /mod_sim_exp/trunk/rtl/
74 removed C_NR_OP and C_NR_M from the generic of mod_sim_exp_core and made them contstants, because currently no other values than 4 an 2 resp. are supported/can be implemented. JonasDC 4090d 00h /mod_sim_exp/trunk/rtl/
73 updated plb interface, mem_style and device generics added JonasDC 4090d 23h /mod_sim_exp/trunk/rtl/
69 big update, the mod_sim_exp core now has a selectable ram structure. a generic ram that should be usable in any fpga, a asymmetric ram that is usable for some devices of altera or xilinx and uses less resources. JonasDC 4091d 23h /mod_sim_exp/trunk/rtl/
67 added memory modules for modulus and operands for FPGA's that support asymmetric memory inferring. JonasDC 4092d 02h /mod_sim_exp/trunk/rtl/
66 added asymmetric ram structures to support a more performant ramstyle.
defined for xilinx and altera, not tested with other tools.		 JonasDC 4092d 03h /mod_sim_exp/trunk/rtl/
65 updated plb interface, now modulus is selectable and, fifo depth is adjustable.
updated makefile with new sources and update component in package		 JonasDC 4099d 18h /mod_sim_exp/trunk/rtl/
63 now using a generic description of the ram for the memory. the core now should synthesize for al fpga's, no device specific code anymore. tested and synthesizes for altera and xilinx JonasDC 4100d 00h /mod_sim_exp/trunk/rtl/
62 not used anymore JonasDC 4100d 03h /mod_sim_exp/trunk/rtl/
61 updated comments, added optional altera constraint JonasDC 4100d 03h /mod_sim_exp/trunk/rtl/
60 generic version of the fifo, not device specific anymore, uses dpram_generic
updated comments of RAM templates.		 JonasDC 4102d 17h /mod_sim_exp/trunk/rtl/
59 added templates that correctly infer RAM, for dual port en true dual port RAM
added general functions file, (used in the two RAM templates)		 JonasDC 4102d 17h /mod_sim_exp/trunk/rtl/
55 updated resource usage in comments JonasDC 4106d 17h /mod_sim_exp/trunk/rtl/
54 generic fifo design: correctrly inferred by xilinx and altera JonasDC 4106d 17h /mod_sim_exp/trunk/rtl/
53 correctly inferred ram for altera dual port ram JonasDC 4107d 00h /mod_sim_exp/trunk/rtl/
52 correct inferring of blockram, no additional resources. JonasDC 4107d 00h /mod_sim_exp/trunk/rtl/
51 true dual port ram for xilinx JonasDC 4107d 01h /mod_sim_exp/trunk/rtl/

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