URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [rtl/] - Rev 82

Rev	Log message	Author	Age	Path
50	added folder for ram descriptions added experimental simple dual port ram implementation for xilinx	JonasDC	4095d 02h	/mod_sim_exp/trunk/rtl/
45	chance run_auto port or mod_sim_exp_core to exp_m	JonasDC	4175d 02h	/mod_sim_exp/trunk/rtl/
44	toplevel of the Modular Simultaneous Exponentiation IP core for the PLB interface	JonasDC	4178d 20h	/mod_sim_exp/trunk/rtl/
43	made the core parameters generics	JonasDC	4178d 20h	/mod_sim_exp/trunk/rtl/
42	corrected wrong library name for mod_sim_exp_pkg	JonasDC	4185d 03h	/mod_sim_exp/trunk/rtl/
41	removed deprecated files from version control	JonasDC	4185d 03h	/mod_sim_exp/trunk/rtl/
40	adjusted core instantiation to new core module name	JonasDC	4193d 07h	/mod_sim_exp/trunk/rtl/
39	changed files to remove warnings from synthesis last cell logic is simplified because of redundant logic	JonasDC	4193d 19h	/mod_sim_exp/trunk/rtl/
38	deprecated design files because of new pipeline structure, will be removed shortly	JonasDC	4194d 00h	/mod_sim_exp/trunk/rtl/
37	changed names of some generics of the multiplier. moved the parameters for the core to the package of the core testbench now uses this parameters to adapt to different bit widths and new systolic pipeline now supports split or single pipeline	JonasDC	4197d 21h	/mod_sim_exp/trunk/rtl/