URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [rtl/] - Rev 88

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

From rev	To rev	Max revs

Search for

Rev	Log message	Author	Age	Path
86	update on previous	JonasDC	4030d 13h	/mod_sim_exp/trunk/rtl
85	changed so that reset now also affects slave register	JonasDC	4030d 13h	/mod_sim_exp/trunk/rtl
84	AXI-Lite interface updated, now tested and verified on Xilinx FPGA renamed C_DEVICE parameter, because of conflicts with restricted parameter in xilinx XPS	JonasDC	4031d 22h	/mod_sim_exp/trunk/rtl
83	now using values from mod_sim_exp_pkg instead of direct entity	JonasDC	4033d 23h	/mod_sim_exp/trunk/rtl
82	added first version of axi-lite interface and testbench for basic axi-lite operations, now under test	JonasDC	4050d 19h	/mod_sim_exp/trunk/rtl
81	updated files, now using the components of the mod_sim_exp_pkg instead of direct entity declaration	JonasDC	4050d 19h	/mod_sim_exp/trunk/rtl
77	found fault in code, now synthesizes normally	JonasDC	4066d 10h	/mod_sim_exp/trunk/rtl
75	made rw_address a vector of a fixed width	JonasDC	4068d 21h	/mod_sim_exp/trunk/rtl
74	removed C_NR_OP and C_NR_M from the generic of mod_sim_exp_core and made them contstants, because currently no other values than 4 an 2 resp. are supported/can be implemented.	JonasDC	4071d 17h	/mod_sim_exp/trunk/rtl
73	updated plb interface, mem_style and device generics added	JonasDC	4072d 17h	/mod_sim_exp/trunk/rtl
69	big update, the mod_sim_exp core now has a selectable ram structure. a generic ram that should be usable in any fpga, a asymmetric ram that is usable for some devices of altera or xilinx and uses less resources.	JonasDC	4073d 17h	/mod_sim_exp/trunk/rtl
67	added memory modules for modulus and operands for FPGA's that support asymmetric memory inferring.	JonasDC	4073d 20h	/mod_sim_exp/trunk/rtl
66	added asymmetric ram structures to support a more performant ramstyle. defined for xilinx and altera, not tested with other tools.	JonasDC	4073d 20h	/mod_sim_exp/trunk/rtl
65	updated plb interface, now modulus is selectable and, fifo depth is adjustable. updated makefile with new sources and update component in package	JonasDC	4081d 12h	/mod_sim_exp/trunk/rtl
63	now using a generic description of the ram for the memory. the core now should synthesize for al fpga's, no device specific code anymore. tested and synthesizes for altera and xilinx	JonasDC	4081d 17h	/mod_sim_exp/trunk/rtl
62	not used anymore	JonasDC	4081d 20h	/mod_sim_exp/trunk/rtl
61	updated comments, added optional altera constraint	JonasDC	4081d 20h	/mod_sim_exp/trunk/rtl
60	generic version of the fifo, not device specific anymore, uses dpram_generic updated comments of RAM templates.	JonasDC	4084d 10h	/mod_sim_exp/trunk/rtl
59	added templates that correctly infer RAM, for dual port en true dual port RAM added general functions file, (used in the two RAM templates)	JonasDC	4084d 11h	/mod_sim_exp/trunk/rtl
55	updated resource usage in comments	JonasDC	4088d 10h	/mod_sim_exp/trunk/rtl

1 2 Next >

Show All

Browse

Tools

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [rtl/] - Rev 88

Filtering Options