URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [rtl/] - Rev 90

Rev	Log message	Author	Age	Path
59	added templates that correctly infer RAM, for dual port en true dual port RAM added general functions file, (used in the two RAM templates)	JonasDC	4087d 21h	/mod_sim_exp/trunk/rtl/
55	updated resource usage in comments	JonasDC	4091d 21h	/mod_sim_exp/trunk/rtl/
54	generic fifo design: correctrly inferred by xilinx and altera	JonasDC	4091d 21h	/mod_sim_exp/trunk/rtl/
53	correctly inferred ram for altera dual port ram	JonasDC	4092d 03h	/mod_sim_exp/trunk/rtl/
52	correct inferring of blockram, no additional resources.	JonasDC	4092d 04h	/mod_sim_exp/trunk/rtl/
51	true dual port ram for xilinx	JonasDC	4092d 04h	/mod_sim_exp/trunk/rtl/
50	added folder for ram descriptions added experimental simple dual port ram implementation for xilinx	JonasDC	4092d 05h	/mod_sim_exp/trunk/rtl/
45	chance run_auto port or mod_sim_exp_core to exp_m	JonasDC	4172d 04h	/mod_sim_exp/trunk/rtl/
44	toplevel of the Modular Simultaneous Exponentiation IP core for the PLB interface	JonasDC	4175d 22h	/mod_sim_exp/trunk/rtl/
43	made the core parameters generics	JonasDC	4175d 22h	/mod_sim_exp/trunk/rtl/