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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] - Rev 30

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4 Modified the architecture, no longer uses Xilinx primitive, instead generic instantiation
added descriptive comments
JonasDC 4427d 23h /mod_sim_exp/trunk/rtl/vhdl/
3 updated vhdl sources with new header according to OC design rules and formated code
added makefile and simulation input file for testbench simulation
JonasDC 4428d 13h /mod_sim_exp/trunk/rtl/vhdl/
2 First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules.. JonasDC 4432d 19h /mod_sim_exp/trunk/rtl/vhdl/

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