URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] - Rev 33

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

From rev	To rev	Max revs

Search for

Rev	Log message	Author	Age	Path
33	default pipeline changed to old version, there seems to be an occasional error with new version.	JonasDC	4213d 18h	/mod_sim_exp/trunk/rtl/vhdl
32	new systolic pipeline structure now has split pipeline support, tested and verified in simulation. the core now uses this pipeline by default.	JonasDC	4213d 19h	/mod_sim_exp/trunk/rtl/vhdl
31	put first cell logic of the pipeline in a separate design unit, tested and working	JonasDC	4214d 00h	/mod_sim_exp/trunk/rtl/vhdl
30	put last cell logic of the pipeline in a separate design unit, tested and working	JonasDC	4214d 01h	/mod_sim_exp/trunk/rtl/vhdl
25	first version of new pipeline design. allows for more flexibility in nr of stages. does not support split pipeline support yet. currently only works for single pipeline	JonasDC	4214d 15h	/mod_sim_exp/trunk/rtl/vhdl
24	changed names of top-level module to mod_sim_exp_core	JonasDC	4218d 00h	/mod_sim_exp/trunk/rtl/vhdl
23	added descriptive comments	JonasDC	4218d 01h	/mod_sim_exp/trunk/rtl/vhdl
22	updated the systolic pipeline with descriptive signal names and comments	JonasDC	4220d 18h	/mod_sim_exp/trunk/rtl/vhdl
21	changed x_i signal to xi	JonasDC	4222d 02h	/mod_sim_exp/trunk/rtl/vhdl
20	added comments, changed signal name of x_reg_i to x_reg. File is now according to OC design rules	JonasDC	4222d 02h	/mod_sim_exp/trunk/rtl/vhdl
19	updated files with descriptive comments changed signal names and removed redundant signals in stepping_logic	JonasDC	4226d 21h	/mod_sim_exp/trunk/rtl/vhdl
18	updated stages with comments and renamed some signals for consistency	JonasDC	4227d 21h	/mod_sim_exp/trunk/rtl/vhdl
17	updated files with descriptive comments and removed unnecessary signals in standard stage. Files are now according to OC design rules	JonasDC	4228d 02h	/mod_sim_exp/trunk/rtl/vhdl
16	package with modified generic parameter for register_n	JonasDC	4228d 15h	/mod_sim_exp/trunk/rtl/vhdl
15	changed generic for register width from n to width for consistency	JonasDC	4228d 15h	/mod_sim_exp/trunk/rtl/vhdl
14	changed comments, file is now according to OC design rules	JonasDC	4228d 15h	/mod_sim_exp/trunk/rtl/vhdl
13	added some descriptive comments and added check for incorrect value's of width and block_width. File is now according to OC design rules	JonasDC	4228d 16h	/mod_sim_exp/trunk/rtl/vhdl
12	updated comments, file is now completely according to design rules	JonasDC	4228d 16h	/mod_sim_exp/trunk/rtl/vhdl
10	changed signal input port names to correct name	JonasDC	4228d 21h	/mod_sim_exp/trunk/rtl/vhdl
9	added descriptive comments, and renamed input mux_result from cell_1b_adder to b for a more generic multipurpose code also renamed output s from n_adder to r, to keep same signal names	JonasDC	4228d 21h	/mod_sim_exp/trunk/rtl/vhdl

1 2 Next >

Show All

Browse

Tools

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] - Rev 33

Filtering Options