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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] - Rev 37

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Rev Log message Author Age Path
37 changed names of some generics of the multiplier.
moved the parameters for the core to the package of the core
testbench now uses this parameters to adapt to different bit widths

and new systolic pipeline now supports split or single pipeline		 JonasDC 4636d 02h /mod_sim_exp/trunk/rtl/vhdl/
36 found bug in new pipeline structure, now working properly. (tested in sim)
mod_sim_exp_core uses new flexible pipeline as default.		 JonasDC 4636d 22h /mod_sim_exp/trunk/rtl/vhdl/
34 operand memory now supports custom operand widths, the internal memory stays the fixed 1536 bit, but the bus width is now adjustable to any size below. JonasDC 4637d 01h /mod_sim_exp/trunk/rtl/vhdl/
33 default pipeline changed to old version, there seems to be an occasional error with new version. JonasDC 4637d 04h /mod_sim_exp/trunk/rtl/vhdl/
32 new systolic pipeline structure now has split pipeline support, tested and verified in simulation. the core now uses this pipeline by default. JonasDC 4637d 05h /mod_sim_exp/trunk/rtl/vhdl/
31 put first cell logic of the pipeline in a separate design unit, tested and working JonasDC 4637d 10h /mod_sim_exp/trunk/rtl/vhdl/
30 put last cell logic of the pipeline in a separate design unit, tested and working JonasDC 4637d 11h /mod_sim_exp/trunk/rtl/vhdl/
25 first version of new pipeline design. allows for more flexibility in nr of stages.
does not support split pipeline support yet. currently only works for single pipeline		 JonasDC 4638d 01h /mod_sim_exp/trunk/rtl/vhdl/
24 changed names of top-level module to mod_sim_exp_core JonasDC 4641d 10h /mod_sim_exp/trunk/rtl/vhdl/
23 added descriptive comments JonasDC 4641d 11h /mod_sim_exp/trunk/rtl/vhdl/
22 updated the systolic pipeline with descriptive signal names and comments JonasDC 4644d 04h /mod_sim_exp/trunk/rtl/vhdl/
21 changed x_i signal to xi JonasDC 4645d 12h /mod_sim_exp/trunk/rtl/vhdl/
20 added comments, changed signal name of x_reg_i to x_reg.
File is now according to OC design rules		 JonasDC 4645d 12h /mod_sim_exp/trunk/rtl/vhdl/
19 updated files with descriptive comments
changed signal names and removed redundant signals in stepping_logic		 JonasDC 4650d 07h /mod_sim_exp/trunk/rtl/vhdl/
18 updated stages with comments and renamed some signals for consistency JonasDC 4651d 07h /mod_sim_exp/trunk/rtl/vhdl/
17 updated files with descriptive comments and removed unnecessary signals in standard stage. Files are now according to OC design rules JonasDC 4651d 12h /mod_sim_exp/trunk/rtl/vhdl/
16 package with modified generic parameter for register_n JonasDC 4652d 01h /mod_sim_exp/trunk/rtl/vhdl/
15 changed generic for register width from n to width for consistency JonasDC 4652d 01h /mod_sim_exp/trunk/rtl/vhdl/
14 changed comments, file is now according to OC design rules JonasDC 4652d 01h /mod_sim_exp/trunk/rtl/vhdl/
13 added some descriptive comments and added check for incorrect value's of width and block_width.
File is now according to OC design rules		 JonasDC 4652d 02h /mod_sim_exp/trunk/rtl/vhdl/

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