Rev |
Log message |
Author |
Age |
Path |
38 |
deprecated design files because of new pipeline structure, will be removed shortly |
JonasDC |
4205d 07h |
/mod_sim_exp/trunk/rtl/vhdl/ |
37 |
changed names of some generics of the multiplier.
moved the parameters for the core to the package of the core
testbench now uses this parameters to adapt to different bit widths
and new systolic pipeline now supports split or single pipeline |
JonasDC |
4209d 04h |
/mod_sim_exp/trunk/rtl/vhdl/ |
36 |
found bug in new pipeline structure, now working properly. (tested in sim)
mod_sim_exp_core uses new flexible pipeline as default. |
JonasDC |
4210d 00h |
/mod_sim_exp/trunk/rtl/vhdl/ |
34 |
operand memory now supports custom operand widths, the internal memory stays the fixed 1536 bit, but the bus width is now adjustable to any size below. |
JonasDC |
4210d 04h |
/mod_sim_exp/trunk/rtl/vhdl/ |
33 |
default pipeline changed to old version, there seems to be an occasional error with new version. |
JonasDC |
4210d 07h |
/mod_sim_exp/trunk/rtl/vhdl/ |
32 |
new systolic pipeline structure now has split pipeline support, tested and verified in simulation. the core now uses this pipeline by default. |
JonasDC |
4210d 08h |
/mod_sim_exp/trunk/rtl/vhdl/ |
31 |
put first cell logic of the pipeline in a separate design unit, tested and working |
JonasDC |
4210d 13h |
/mod_sim_exp/trunk/rtl/vhdl/ |
30 |
put last cell logic of the pipeline in a separate design unit, tested and working |
JonasDC |
4210d 13h |
/mod_sim_exp/trunk/rtl/vhdl/ |
25 |
first version of new pipeline design. allows for more flexibility in nr of stages.
does not support split pipeline support yet. currently only works for single pipeline |
JonasDC |
4211d 03h |
/mod_sim_exp/trunk/rtl/vhdl/ |
24 |
changed names of top-level module to mod_sim_exp_core |
JonasDC |
4214d 12h |
/mod_sim_exp/trunk/rtl/vhdl/ |
23 |
added descriptive comments |
JonasDC |
4214d 13h |
/mod_sim_exp/trunk/rtl/vhdl/ |
22 |
updated the systolic pipeline with descriptive signal names and comments |
JonasDC |
4217d 07h |
/mod_sim_exp/trunk/rtl/vhdl/ |
21 |
changed x_i signal to xi |
JonasDC |
4218d 14h |
/mod_sim_exp/trunk/rtl/vhdl/ |
20 |
added comments, changed signal name of x_reg_i to x_reg.
File is now according to OC design rules |
JonasDC |
4218d 15h |
/mod_sim_exp/trunk/rtl/vhdl/ |
19 |
updated files with descriptive comments
changed signal names and removed redundant signals in stepping_logic |
JonasDC |
4223d 10h |
/mod_sim_exp/trunk/rtl/vhdl/ |
18 |
updated stages with comments and renamed some signals for consistency |
JonasDC |
4224d 09h |
/mod_sim_exp/trunk/rtl/vhdl/ |
17 |
updated files with descriptive comments and removed unnecessary signals in standard stage. Files are now according to OC design rules |
JonasDC |
4224d 14h |
/mod_sim_exp/trunk/rtl/vhdl/ |
16 |
package with modified generic parameter for register_n |
JonasDC |
4225d 03h |
/mod_sim_exp/trunk/rtl/vhdl/ |
15 |
changed generic for register width from n to width for consistency |
JonasDC |
4225d 03h |
/mod_sim_exp/trunk/rtl/vhdl/ |
14 |
changed comments, file is now according to OC design rules |
JonasDC |
4225d 04h |
/mod_sim_exp/trunk/rtl/vhdl/ |