URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] - Rev 40

Rev	Log message	Author	Age	Path
15	changed generic for register width from n to width for consistency	JonasDC	4202d 16h	/mod_sim_exp/trunk/rtl/vhdl/
14	changed comments, file is now according to OC design rules	JonasDC	4202d 16h	/mod_sim_exp/trunk/rtl/vhdl/
13	added some descriptive comments and added check for incorrect value's of width and block_width. File is now according to OC design rules	JonasDC	4202d 17h	/mod_sim_exp/trunk/rtl/vhdl/
12	updated comments, file is now completely according to design rules	JonasDC	4202d 17h	/mod_sim_exp/trunk/rtl/vhdl/
10	changed signal input port names to correct name	JonasDC	4202d 22h	/mod_sim_exp/trunk/rtl/vhdl/
9	added descriptive comments, and renamed input mux_result from cell_1b_adder to b for a more generic multipurpose code also renamed output s from n_adder to r, to keep same signal names	JonasDC	4202d 22h	/mod_sim_exp/trunk/rtl/vhdl/
8	added descriptive comments	JonasDC	4203d 00h	/mod_sim_exp/trunk/rtl/vhdl/
7	Modified the architecture, no longer uses Xilinx primitive, instead generic instantiation added descriptive comments	JonasDC	4203d 00h	/mod_sim_exp/trunk/rtl/vhdl/
6	Modified the architecture, no longer uses Xilinx primitive, instead generic instantiation added descriptive comments	JonasDC	4203d 00h	/mod_sim_exp/trunk/rtl/vhdl/
4	Modified the architecture, no longer uses Xilinx primitive, instead generic instantiation added descriptive comments	JonasDC	4203d 02h	/mod_sim_exp/trunk/rtl/vhdl/