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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] - Rev 50

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Rev	Log message	Author	Age	Path
50	added folder for ram descriptions added experimental simple dual port ram implementation for xilinx	JonasDC	4089d 17h	/mod_sim_exp/trunk/rtl/vhdl
45	chance run_auto port or mod_sim_exp_core to exp_m	JonasDC	4169d 17h	/mod_sim_exp/trunk/rtl/vhdl
44	toplevel of the Modular Simultaneous Exponentiation IP core for the PLB interface	JonasDC	4173d 10h	/mod_sim_exp/trunk/rtl/vhdl
43	made the core parameters generics	JonasDC	4173d 10h	/mod_sim_exp/trunk/rtl/vhdl
42	corrected wrong library name for mod_sim_exp_pkg	JonasDC	4179d 18h	/mod_sim_exp/trunk/rtl/vhdl
41	removed deprecated files from version control	JonasDC	4179d 18h	/mod_sim_exp/trunk/rtl/vhdl
40	adjusted core instantiation to new core module name	JonasDC	4187d 22h	/mod_sim_exp/trunk/rtl/vhdl
39	changed files to remove warnings from synthesis last cell logic is simplified because of redundant logic	JonasDC	4188d 09h	/mod_sim_exp/trunk/rtl/vhdl
38	deprecated design files because of new pipeline structure, will be removed shortly	JonasDC	4188d 15h	/mod_sim_exp/trunk/rtl/vhdl
37	changed names of some generics of the multiplier. moved the parameters for the core to the package of the core testbench now uses this parameters to adapt to different bit widths and new systolic pipeline now supports split or single pipeline	JonasDC	4192d 12h	/mod_sim_exp/trunk/rtl/vhdl
36	found bug in new pipeline structure, now working properly. (tested in sim) mod_sim_exp_core uses new flexible pipeline as default.	JonasDC	4193d 08h	/mod_sim_exp/trunk/rtl/vhdl
34	operand memory now supports custom operand widths, the internal memory stays the fixed 1536 bit, but the bus width is now adjustable to any size below.	JonasDC	4193d 12h	/mod_sim_exp/trunk/rtl/vhdl
33	default pipeline changed to old version, there seems to be an occasional error with new version.	JonasDC	4193d 14h	/mod_sim_exp/trunk/rtl/vhdl
32	new systolic pipeline structure now has split pipeline support, tested and verified in simulation. the core now uses this pipeline by default.	JonasDC	4193d 15h	/mod_sim_exp/trunk/rtl/vhdl
31	put first cell logic of the pipeline in a separate design unit, tested and working	JonasDC	4193d 21h	/mod_sim_exp/trunk/rtl/vhdl
30	put last cell logic of the pipeline in a separate design unit, tested and working	JonasDC	4193d 21h	/mod_sim_exp/trunk/rtl/vhdl
25	first version of new pipeline design. allows for more flexibility in nr of stages. does not support split pipeline support yet. currently only works for single pipeline	JonasDC	4194d 11h	/mod_sim_exp/trunk/rtl/vhdl
24	changed names of top-level module to mod_sim_exp_core	JonasDC	4197d 20h	/mod_sim_exp/trunk/rtl/vhdl
23	added descriptive comments	JonasDC	4197d 21h	/mod_sim_exp/trunk/rtl/vhdl
22	updated the systolic pipeline with descriptive signal names and comments	JonasDC	4200d 15h	/mod_sim_exp/trunk/rtl/vhdl

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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] - Rev 50

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