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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] - Rev 55

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Rev Log message Author Age Path
55 updated resource usage in comments JonasDC 4671d 23h /mod_sim_exp/trunk/rtl/vhdl/
54 generic fifo design: correctrly inferred by xilinx and altera JonasDC 4672d 00h /mod_sim_exp/trunk/rtl/vhdl/
53 correctly inferred ram for altera dual port ram JonasDC 4672d 06h /mod_sim_exp/trunk/rtl/vhdl/
52 correct inferring of blockram, no additional resources. JonasDC 4672d 07h /mod_sim_exp/trunk/rtl/vhdl/
51 true dual port ram for xilinx JonasDC 4672d 07h /mod_sim_exp/trunk/rtl/vhdl/
50 added folder for ram descriptions
added experimental simple dual port ram implementation for xilinx		 JonasDC 4672d 07h /mod_sim_exp/trunk/rtl/vhdl/
45 chance run_auto port or mod_sim_exp_core to exp_m JonasDC 4752d 07h /mod_sim_exp/trunk/rtl/vhdl/
44 toplevel of the Modular Simultaneous Exponentiation IP core for the PLB interface JonasDC 4756d 01h /mod_sim_exp/trunk/rtl/vhdl/
43 made the core parameters generics JonasDC 4756d 01h /mod_sim_exp/trunk/rtl/vhdl/
42 corrected wrong library name for mod_sim_exp_pkg JonasDC 4762d 09h /mod_sim_exp/trunk/rtl/vhdl/
41 removed deprecated files from version control JonasDC 4762d 09h /mod_sim_exp/trunk/rtl/vhdl/
40 adjusted core instantiation to new core module name JonasDC 4770d 13h /mod_sim_exp/trunk/rtl/vhdl/
39 changed files to remove warnings from synthesis
last cell logic is simplified because of redundant logic		 JonasDC 4771d 00h /mod_sim_exp/trunk/rtl/vhdl/
38 deprecated design files because of new pipeline structure, will be removed shortly JonasDC 4771d 05h /mod_sim_exp/trunk/rtl/vhdl/
37 changed names of some generics of the multiplier.
moved the parameters for the core to the package of the core
testbench now uses this parameters to adapt to different bit widths

and new systolic pipeline now supports split or single pipeline		 JonasDC 4775d 02h /mod_sim_exp/trunk/rtl/vhdl/
36 found bug in new pipeline structure, now working properly. (tested in sim)
mod_sim_exp_core uses new flexible pipeline as default.		 JonasDC 4775d 23h /mod_sim_exp/trunk/rtl/vhdl/
34 operand memory now supports custom operand widths, the internal memory stays the fixed 1536 bit, but the bus width is now adjustable to any size below. JonasDC 4776d 02h /mod_sim_exp/trunk/rtl/vhdl/
33 default pipeline changed to old version, there seems to be an occasional error with new version. JonasDC 4776d 05h /mod_sim_exp/trunk/rtl/vhdl/
32 new systolic pipeline structure now has split pipeline support, tested and verified in simulation. the core now uses this pipeline by default. JonasDC 4776d 06h /mod_sim_exp/trunk/rtl/vhdl/
31 put first cell logic of the pipeline in a separate design unit, tested and working JonasDC 4776d 11h /mod_sim_exp/trunk/rtl/vhdl/

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