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Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] - Rev 68

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Rev	Log message	Author	Age	Path
39	changed files to remove warnings from synthesis last cell logic is simplified because of redundant logic	JonasDC	4193d 02h	/mod_sim_exp/trunk/rtl/vhdl/
38	deprecated design files because of new pipeline structure, will be removed shortly	JonasDC	4193d 08h	/mod_sim_exp/trunk/rtl/vhdl/
37	changed names of some generics of the multiplier. moved the parameters for the core to the package of the core testbench now uses this parameters to adapt to different bit widths and new systolic pipeline now supports split or single pipeline	JonasDC	4197d 05h	/mod_sim_exp/trunk/rtl/vhdl/
36	found bug in new pipeline structure, now working properly. (tested in sim) mod_sim_exp_core uses new flexible pipeline as default.	JonasDC	4198d 01h	/mod_sim_exp/trunk/rtl/vhdl/
34	operand memory now supports custom operand widths, the internal memory stays the fixed 1536 bit, but the bus width is now adjustable to any size below.	JonasDC	4198d 05h	/mod_sim_exp/trunk/rtl/vhdl/
33	default pipeline changed to old version, there seems to be an occasional error with new version.	JonasDC	4198d 08h	/mod_sim_exp/trunk/rtl/vhdl/
32	new systolic pipeline structure now has split pipeline support, tested and verified in simulation. the core now uses this pipeline by default.	JonasDC	4198d 09h	/mod_sim_exp/trunk/rtl/vhdl/
31	put first cell logic of the pipeline in a separate design unit, tested and working	JonasDC	4198d 14h	/mod_sim_exp/trunk/rtl/vhdl/
30	put last cell logic of the pipeline in a separate design unit, tested and working	JonasDC	4198d 14h	/mod_sim_exp/trunk/rtl/vhdl/
25	first version of new pipeline design. allows for more flexibility in nr of stages. does not support split pipeline support yet. currently only works for single pipeline	JonasDC	4199d 04h	/mod_sim_exp/trunk/rtl/vhdl/

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