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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] - Rev 73

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Rev Log message Author Age Path
73 updated plb interface, mem_style and device generics added JonasDC 3737d 07h /mod_sim_exp/trunk/rtl/vhdl/
69 big update, the mod_sim_exp core now has a selectable ram structure. a generic ram that should be usable in any fpga, a asymmetric ram that is usable for some devices of altera or xilinx and uses less resources. JonasDC 3738d 07h /mod_sim_exp/trunk/rtl/vhdl/
67 added memory modules for modulus and operands for FPGA's that support asymmetric memory inferring. JonasDC 3738d 10h /mod_sim_exp/trunk/rtl/vhdl/
66 added asymmetric ram structures to support a more performant ramstyle.
defined for xilinx and altera, not tested with other tools.
JonasDC 3738d 10h /mod_sim_exp/trunk/rtl/vhdl/
65 updated plb interface, now modulus is selectable and, fifo depth is adjustable.
updated makefile with new sources and update component in package
JonasDC 3746d 02h /mod_sim_exp/trunk/rtl/vhdl/
63 now using a generic description of the ram for the memory. the core now should synthesize for al fpga's, no device specific code anymore. tested and synthesizes for altera and xilinx JonasDC 3746d 08h /mod_sim_exp/trunk/rtl/vhdl/
62 not used anymore JonasDC 3746d 11h /mod_sim_exp/trunk/rtl/vhdl/
61 updated comments, added optional altera constraint JonasDC 3746d 11h /mod_sim_exp/trunk/rtl/vhdl/
60 generic version of the fifo, not device specific anymore, uses dpram_generic
updated comments of RAM templates.
JonasDC 3749d 01h /mod_sim_exp/trunk/rtl/vhdl/
59 added templates that correctly infer RAM, for dual port en true dual port RAM
added general functions file, (used in the two RAM templates)
JonasDC 3749d 01h /mod_sim_exp/trunk/rtl/vhdl/
55 updated resource usage in comments JonasDC 3753d 01h /mod_sim_exp/trunk/rtl/vhdl/
54 generic fifo design: correctrly inferred by xilinx and altera JonasDC 3753d 01h /mod_sim_exp/trunk/rtl/vhdl/
53 correctly inferred ram for altera dual port ram JonasDC 3753d 08h /mod_sim_exp/trunk/rtl/vhdl/
52 correct inferring of blockram, no additional resources. JonasDC 3753d 08h /mod_sim_exp/trunk/rtl/vhdl/
51 true dual port ram for xilinx JonasDC 3753d 09h /mod_sim_exp/trunk/rtl/vhdl/
50 added folder for ram descriptions
added experimental simple dual port ram implementation for xilinx
JonasDC 3753d 09h /mod_sim_exp/trunk/rtl/vhdl/
45 chance run_auto port or mod_sim_exp_core to exp_m JonasDC 3833d 09h /mod_sim_exp/trunk/rtl/vhdl/
44 toplevel of the Modular Simultaneous Exponentiation IP core for the PLB interface JonasDC 3837d 02h /mod_sim_exp/trunk/rtl/vhdl/
43 made the core parameters generics JonasDC 3837d 02h /mod_sim_exp/trunk/rtl/vhdl/
42 corrected wrong library name for mod_sim_exp_pkg JonasDC 3843d 10h /mod_sim_exp/trunk/rtl/vhdl/

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