URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] - Rev 75

Rev	Log message	Author	Age	Path
43	made the core parameters generics	JonasDC	4174d 04h	/mod_sim_exp/trunk/rtl/vhdl/
42	corrected wrong library name for mod_sim_exp_pkg	JonasDC	4180d 12h	/mod_sim_exp/trunk/rtl/vhdl/
41	removed deprecated files from version control	JonasDC	4180d 12h	/mod_sim_exp/trunk/rtl/vhdl/
40	adjusted core instantiation to new core module name	JonasDC	4188d 16h	/mod_sim_exp/trunk/rtl/vhdl/
39	changed files to remove warnings from synthesis last cell logic is simplified because of redundant logic	JonasDC	4189d 03h	/mod_sim_exp/trunk/rtl/vhdl/
38	deprecated design files because of new pipeline structure, will be removed shortly	JonasDC	4189d 09h	/mod_sim_exp/trunk/rtl/vhdl/
37	changed names of some generics of the multiplier. moved the parameters for the core to the package of the core testbench now uses this parameters to adapt to different bit widths and new systolic pipeline now supports split or single pipeline	JonasDC	4193d 06h	/mod_sim_exp/trunk/rtl/vhdl/
36	found bug in new pipeline structure, now working properly. (tested in sim) mod_sim_exp_core uses new flexible pipeline as default.	JonasDC	4194d 02h	/mod_sim_exp/trunk/rtl/vhdl/
34	operand memory now supports custom operand widths, the internal memory stays the fixed 1536 bit, but the bus width is now adjustable to any size below.	JonasDC	4194d 05h	/mod_sim_exp/trunk/rtl/vhdl/
33	default pipeline changed to old version, there seems to be an occasional error with new version.	JonasDC	4194d 08h	/mod_sim_exp/trunk/rtl/vhdl/