Rev |
Log message |
Author |
Age |
Path |
90 |
reverted changes from previous revision, updated AXI version with testbench |
JonasDC |
3978d 01h |
/mod_sim_exp/trunk/rtl/vhdl |
89 |
updated vhdl files so now different clock frequencies are posible for the core and bus interface. |
JonasDC |
4041d 23h |
/mod_sim_exp/trunk/rtl/vhdl |
86 |
update on previous |
JonasDC |
4048d 01h |
/mod_sim_exp/trunk/rtl/vhdl |
85 |
changed so that reset now also affects slave register |
JonasDC |
4048d 01h |
/mod_sim_exp/trunk/rtl/vhdl |
84 |
AXI-Lite interface updated, now tested and verified on Xilinx FPGA
renamed C_DEVICE parameter, because of conflicts with restricted parameter in xilinx XPS |
JonasDC |
4049d 09h |
/mod_sim_exp/trunk/rtl/vhdl |
83 |
now using values from mod_sim_exp_pkg instead of direct entity |
JonasDC |
4051d 10h |
/mod_sim_exp/trunk/rtl/vhdl |
82 |
added first version of axi-lite interface and testbench for basic axi-lite operations, now under test |
JonasDC |
4068d 06h |
/mod_sim_exp/trunk/rtl/vhdl |
81 |
updated files, now using the components of the mod_sim_exp_pkg instead of direct entity declaration |
JonasDC |
4068d 06h |
/mod_sim_exp/trunk/rtl/vhdl |
77 |
found fault in code, now synthesizes normally |
JonasDC |
4083d 22h |
/mod_sim_exp/trunk/rtl/vhdl |
75 |
made rw_address a vector of a fixed width |
JonasDC |
4086d 09h |
/mod_sim_exp/trunk/rtl/vhdl |
74 |
removed C_NR_OP and C_NR_M from the generic of mod_sim_exp_core and made them contstants, because currently no other values than 4 an 2 resp. are supported/can be implemented. |
JonasDC |
4089d 05h |
/mod_sim_exp/trunk/rtl/vhdl |
73 |
updated plb interface, mem_style and device generics added |
JonasDC |
4090d 04h |
/mod_sim_exp/trunk/rtl/vhdl |
69 |
big update, the mod_sim_exp core now has a selectable ram structure. a generic ram that should be usable in any fpga, a asymmetric ram that is usable for some devices of altera or xilinx and uses less resources. |
JonasDC |
4091d 04h |
/mod_sim_exp/trunk/rtl/vhdl |
67 |
added memory modules for modulus and operands for FPGA's that support asymmetric memory inferring. |
JonasDC |
4091d 07h |
/mod_sim_exp/trunk/rtl/vhdl |
66 |
added asymmetric ram structures to support a more performant ramstyle.
defined for xilinx and altera, not tested with other tools. |
JonasDC |
4091d 07h |
/mod_sim_exp/trunk/rtl/vhdl |
65 |
updated plb interface, now modulus is selectable and, fifo depth is adjustable.
updated makefile with new sources and update component in package |
JonasDC |
4098d 23h |
/mod_sim_exp/trunk/rtl/vhdl |
63 |
now using a generic description of the ram for the memory. the core now should synthesize for al fpga's, no device specific code anymore. tested and synthesizes for altera and xilinx |
JonasDC |
4099d 05h |
/mod_sim_exp/trunk/rtl/vhdl |
62 |
not used anymore |
JonasDC |
4099d 07h |
/mod_sim_exp/trunk/rtl/vhdl |
61 |
updated comments, added optional altera constraint |
JonasDC |
4099d 07h |
/mod_sim_exp/trunk/rtl/vhdl |
60 |
generic version of the fifo, not device specific anymore, uses dpram_generic
updated comments of RAM templates. |
JonasDC |
4101d 22h |
/mod_sim_exp/trunk/rtl/vhdl |